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Patrick H Carberry

from East Greenville, PA
Age ~55
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Also known as:
Patrick Henry Carberry
Phone and address:
1040 Church Rd, East Greenville, PA 18041
(215) 679-8251
Related to:
Mary Lou Carberry, 84Martin F Carberry, 61
Connected to:
Christina A Carberry, 30Larry W Carberry, 51Genevieve R Carbery, 110Kevin B Carbery, 62Monica A Carbery, 55Pete B Carbery, 79Thomas J Carbery, 61Reina M Carbetta, 50Francisco Carbia, 85Louis W Carbins, 45

Patrick Carberry Phones & Addresses

  • 1040 Church Rd, East Greenville, PA 18041 (215) 679-8251
  • 269 Church Rd, East Greenville, PA 18041
  • E Greenville, PA
  • 197 W Reliance Rd #1, Telford, PA 18969 (215) 679-8251
  • 401 Summit St, Telford, PA 18969 (215) 703-0106
  • 401 E Summit St #91, Telford, PA 18969
  • 91 Meadow Glen St, Telford, PA 18969
  • 661 89Th Ave, Fort Lauderdale, FL 33324 (954) 370-6152 (215) 679-8251
  • 1300 126Th Ave, Fort Lauderdale, FL 33323 (954) 846-9219
  • Plantation, FL
  • 1 Lindenwald Ter #2, Ambler, PA 19002 (215) 679-8251
  • 1040 Church Rd, E Greenville, PA 18041 (215) 262-2536

Work

Position: Protective Service Occupations

Education

Degree: Graduate or professional degree

Industries

Semiconductors

Resumes

Resumes

Patrick Carberry Photo 1

Semiconductors Professional

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Location:
Allentown, Pennsylvania Area
Industry:
Semiconductors

Publications

Isbn (Books And Publications)

Cad/Cam With Personal Computers

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Author

Patrick R. Carberry

ISBN #

0830608524

Us Patents

Semiconductor Device Package With Reduced Leakage

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US Patent:
7224047, May 29, 2007
Filed:
Dec 18, 2004
Appl. No.:
11/015534
Inventors:
Patrick Joseph Carberry - Laurys Station PA, US
Jeffery John Gilbert - Schwenksville PA, US
Ralph Salvatore Moyer - Robesonia PA, US
John William Osenbach - Kutztown PA, US
Hugo Fernando Safar - Westfield NJ, US
Thomas Herbert Shilling - Macungie PA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H01L 23/495
H01L 23/02
H01L 23/28
H01L 23/34
H01L 33/00
US Classification:
257676, 257E33075, 257E3373, 257E33057, 257 99, 257433, 257675, 257696, 257712, 257704, 257707, 257706, 257710, 257713, 257680, 257795, 257784, 257786
Abstract:
A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Electrical Devices Having Adjustable Electrical Characteristics

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US Patent:
7456716, Nov 25, 2008
Filed:
Dec 24, 2003
Appl. No.:
10/746824
Inventors:
Patrick J. Carberry - Laurys Station PA, US
Jeffery J. Gilbert - Schwenksville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01F 30/14
US Classification:
336 10
Abstract:
Electrical devices having tunable electrical characteristics are provided, such as variable resistors, capacitors and inductors. The tunable electrical characteristics are achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the electrical characteristics of the electrical device. The composition, shape and dimension of the embedded materials determine how the electrical characteristics of the electrical device are altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the electrical characteristics of the integrated electrical device is altered.

Semiconductor Device Package With Base Features To Reduce Leakage

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US Patent:
7541669, Jun 2, 2009
Filed:
Apr 19, 2007
Appl. No.:
11/788346
Inventors:
Patrick Joseph Carberry - Laurys Station PA, US
Jeffery John Gilbert - Schwenksville PA, US
Ralph Salvatore Moyer - Robesonia PA, US
John William Osenbach - Kutztown PA, US
Hugo Fernando Safar - Westfield NJ, US
Thomas Herbert Shilling - Macungie PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 33/00
H01L 23/495
H01L 23/28
H01L 23/34
US Classification:
257676, 257E33075, 257675, 257E33057, 257 99, 257433, 257696, 257712, 257704, 257707, 257706, 257710, 257713, 257680, 257795, 257784, 257786
Abstract:
A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Packages For Encapsulated Semiconductor Devices And Method Of Making Same

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US Patent:
7956451, Jun 7, 2011
Filed:
Dec 18, 2004
Appl. No.:
11/015535
Inventors:
Patrick Joseph Carberry - Laurys Station PA, US
Jeffery John Gilbert - Schwenksville PA, US
Ralph Salvatore Moyer - Robesonia PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 31/08
US Classification:
257687, 257787, 257790, 257668, 257676, 257E2314
Abstract:
A semiconductor device package comprises a container having a base and side walls of an electrically insulating material. A semiconductor device chip is disposed on the base, and a lead frame extends through the side walls. At least one electrical conductor couples the lead frame to the chip. A first layer of an electrically insulating cured gel covers the chip and the lead frame, and a second layer of an electrically insulating cured gel covers at least the portion of the first layer that covers the chip, but does not extend to the side walls. In one embodiment, the second layer has the shape of a dome. In a preferred embodiment the gel comprises silicone. In another embodiment a third layer of conformal insulating material is disposed on the second layer and essentially fills the container. Also is described is a method of making the package for use with RFLDMOS chips.

Electrical Devices Having Adjustable Capacitance

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US Patent:
7960812, Jun 14, 2011
Filed:
Oct 17, 2008
Appl. No.:
12/253403
Inventors:
Patrick J. Carberry - Laurys Station PA, US
Jeffery J. Gilbert - Schwenksville PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H01L 29/84
US Classification:
257532, 257E29324, 257E29342
Abstract:
Electrical devices having tunable capacitance are provided. The tunable capacitance is achieved by placing an appropriate material between substrate layers and by controllably applying a pressure to the material to compress the material or alter the shape of a well in which the material is contained, and thereby alter the capacitance of the electrical device. The composition, shape and dimension of the embedded materials determine how the capacitance of the electrical device is altered upon compression of the embedded material in response to an applied control signal. Generally, as the embedded material is compressed, the material will become more dense and the capacitance of the integrated electrical device is altered.

Process For Fabricating A Power Hybrid Module

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US Patent:
20040212081, Oct 28, 2004
Filed:
Apr 8, 2003
Appl. No.:
10/408448
Inventors:
Patrick Carberry - Allentown PA, US
Lawrence Golick - Allentown PA, US
Juan Herbsommer - Berkeley Heights NJ, US
Osvaldo Lopez - Lebenon NJ, US
Michael Quinn - Allentown PA, US
Hugo Safar - Berkeley Heights NJ, US
International Classification:
H01L023/34
US Classification:
257/717000
Abstract:
A process for fabricating a power hybrid module including placing at least one carrier assembly in at least one opening in at least one printed circuit board, mounting the at least one carrier assembly and the at least one printed circuit board on assembly tape, electrically connecting one of the at least one carrier assemblies and one of the at least one printed circuit boards, overmolding the at least one carrier assembly and the at least one printed circuit board and removing the assembly tape to produce a surface mount power hybrid module. A power hybrid module including at least one printed circuit board with at least one opening therein, at least one carrier assembly, positioned in the at least one opening such that said at least one carrier assembly may be surface mounted and electrically connected to the at least one printed circuit board, and an overmold over the at least one printed circuit board and the at least one carrier assembly.

Methods And Apparatus For Integrated Circuit Ball Bonding Using Stacked Ball Bumps

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US Patent:
20060001157, Jan 5, 2006
Filed:
Jun 30, 2004
Appl. No.:
10/881191
Inventors:
Patrick Carberry - Laurys Station PA, US
International Classification:
H01L 23/48
US Classification:
257738000, 257750000
Abstract:
An integrated circuit comprises at least one circuit element having at least one bond site and a passivation layer. The bond site is accessible through an aperture in the passivation layer. At least two ball bumps are disposed at the bond site. A first ball bump is bonded to the bond site, and each additional ball bump is bonded on a previously bonded ball bump so that the height of the ball bumps is greater than the thickness of the passivation layer above the bond site. A ball bond is bonded to an uppermost ball bump and has a wire formed integrally therewith.

Leadframe Designs For Plastic Cavity Transistor Packages

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US Patent:
20060145317, Jul 6, 2006
Filed:
Dec 31, 2004
Appl. No.:
11/029254
Inventors:
John Brennan - Wyomissing NY, US
Patrick Carberry - Laurys Station PA, US
Jeffery Gilbert - Schwenksville PA, US
George Libricz - Bethlehem PA, US
Ralph Moyer - Robesonia PA, US
John Osenbach - Kutztown PA, US
International Classification:
H01L 21/44
H01L 23/495
US Classification:
257676000, 438123000, 257669000
Abstract:
The specification describes a plastic cavity package for semiconductor devices that provides additional mechanical integrity for leads that extend from the plastic housing. Portions of the leads that are within the plastic housing are provided with cutouts. When the plastic housing is formed, or when the cavity is filled with polymer, plastic material fills the cutout, and joins to the mass of plastic on either side of the cutout, thus forming a continuous integral mass of plastic. The end result is that the plastic in the cutout, coupled to the main plastic mass, and to the rigid package sidewall, forms an effective anchor against pulling and bending forces the leads may encounter in manufacture or use.
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Patrick H Carberry from East Greenville, PA, age ~55 Get Report