Patrick E Connor

6430628, Aug 6, 2002

Dec 8, 1998

09/207461

Patrick Connor - Portland OR

Intel Corporation - Santa Clara CA

G06F 300

710 5, 710 23, 710 56

One embodiment of the invention comprises a method and apparatus for managing data transfers from memory to an input/output device where the data is stored in memory as data fragments. A first list of memory locations for the fragments is received. A sub-set of fragments for copying to at least one of a first and second buffer is selected based on fragment size. A request to copy the selected sub-set of fragments to the at least one first and second buffer is sent. A request to lock down any unselected fragments is sent. A second list of memory locations for the fragments is created. The second list comprises memory locations for the at least one first and second buffer and locked down fragments.

6633941, Oct 14, 2003

Sep 25, 2002

10/255525

Randall D. Dunlap - Portland OR
Patrick L. Connor - Portland OR
John A. Ronciak - Beaverton OR
Greg D. Cummings - Portland OR
Gary G. Li - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 1324

710262, 710 48, 710260, 710261, 710263, 710264, 710266, 710268, 709101, 712244

An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

6647438, Nov 11, 2003

Sep 19, 2000

09/663957

Patrick L. Connor - Portland OR
Robert G. McVay - Portland OR

Intel Corporation - Santa Clara CA

G06F 1328

710 22, 710 30, 710 52, 710 36, 370400

Direct memory access (DMA) transfers to read data from memory are reduced by overlaying data into an immediate data space of a descriptor ring. The descriptor ring includes a context descriptor that points to the data overlaid into the immediate data space. This data space contains smaller blocks of data, such as header or control information for a packet/frame. The descriptor ring further includes scatter gather descriptors that point to data buffers outside of the descriptor ring. These data buffers contain larger blocks of data, such as payload data of the packet/frame. The scatter gather descriptor(s), context descriptor(s), and immediate data space(s) are arranged contiguously in the descriptor ring to allow the descriptor ring to be read in a single direct memory access (DMA) transfer or burst.

6681275, Jan 20, 2004

Sep 20, 2001

09/961108

Patrick L. Connor - Portland OR
David S. Feldman - North Plains OR

Intel Corporation - Santa Clara CA

G06F 1310

710 58, 710 15, 710 16, 710 18, 710 60, 709223

Numerous embodiments of a method and apparatus for dynamic coalescing are disclosed.

6721835, Apr 13, 2004

Sep 19, 2000

09/663953

Patrick L. Connor - Portland OR

Intel Corporation - Santa Clara CA

G06F 1200

710240

While a controller is reading a frame, a driver prepares one or more subsequent frames. A single inform write is sent by the driver to a command register of the controller to inform the controller of completion of preparation of the subsequent frame(s). By preparing the subsequent frame(s) during the reading of the frame and by collectively batching the inform writes of the prepared subsequent frames as the single inform write, instead of sending separate individual inform writes, the reading of frame(s) by the controller is uninterrupted and a number of times that the controller has to arbitrate for bus control is minimized. This advantageously reduces bus contention and latency.

6735662, May 11, 2004

Sep 19, 2000

09/663952

Patrick L. Connor - Portland OR

Intel Corporation - Santa Clara CA

G06F 1336

710308, 710305, 710 22, 710 30, 370473, 709236

A single completion status write back is generated by a controller to inform a driver of completion of a transmission of all frames of an array of frames, as opposed to generating individual write backs for each frame. The driver identifies one of the frames that is reported with the completion status, and applies the completion status to that frame and to all frames of the array sent prior to that frame. Reducing the number of these overhead completion status write backs improves bus and data transfer efficiency.

6760799, Jul 6, 2004

Sep 30, 1999

09/409626

Randall D. Dunlap - Portland OR
Patrick L. Connor - Portland OR
John A. Ronciak - Beaverton OR
Greg D. Cummings - Portland OR
Gary G. Li - Beaverton OR

Intel Corporation - Santa Clara CA

G06F 1324

710260, 710 18, 710 48, 710 52, 710261, 710262, 710263, 710264, 710266, 710268, 718101, 712244

An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.

6779070, Aug 17, 2004

Dec 12, 2001

10/017538

Patrick L. Connor - Portland OR
Patrick J. Luhmann - Hillsboro OR

Intel Corporation - Santa Clara CA

G06F 1314

710315, 710313

The present disclosure relates to a method and apparatus to improve the transmission of data between two or more buses, wherein a bridge is used to predict a characteristic of a data transaction that occurs between a first bus, which utilizes a protocol that does not supply the characteristic, and a second bus, which utilizes a protocol that may make use of this information.