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Patrick J Knebel

from Fort Collins, CO
Age ~60
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Also known as:
Patrick E Knebel, Patrick R Knebel, Pat J Knebel
Phone and address:
2201 Greenmont Ct, Fort Collins, CO 80524
(970) 490-1703
Related to:
Carl J Knebel, 95
Connected to:
Christina M Knebel, 32Harold J Knebel, 101Hyo T Knebel, 68Lindsey A Knebel, 36Norbert J Knebel, 98Helmut Knebl, 76Robert L Knechel, 55Betsy S KnechtBeverly G Knecht, 84Caitlin Knecht, 34

Patrick Knebel Phones & Addresses

  • 2201 Greenmont Ct, Fort Collins, CO 80524 (970) 490-1703
  • Red Feather Lakes, CO

Work

Company: Hewlett-packard Jun 1986 Position: Hpe fellow and vice president

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Stanford University

Industries

Information Technology And Services

Resumes

Resumes

Patrick Knebel Photo 1

Hpe Fellow And Vice President

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Location:
Fort Collins, CO
Industry:
Information Technology And Services
Work:
Hewlett-Packard
Hpe Fellow and Vice President
Education:
Stanford University
Masters, Master of Science In Electrical Engineering Purdue University
Bachelors, Bachelor of Science In Electrical Engineering

Publications

Us Patents

Determining Register Dependency In Multiple Architecture Systems

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US Patent:
6542862, Apr 1, 2003
Filed:
Feb 18, 2000
Appl. No.:
09/506776
Inventors:
Kevin David Safford - Fort Collins CO
Patrick Knebel - Ft Collins CO
Joel D Lamb - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9445
US Classification:
703 26, 703 14, 712 24, 712 32, 712204, 712212, 712217
Abstract:
An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides the native instructions where each native instruction contains at least one register identifier. Flags are provided to each native instruction where each flag indicates whether a register identifier is valid. A bundler checks for dependency among the valid register identifiers in the native instructions.

Method And Apparatus For Implementing Two Architectures In A Chip Using Bundles That Contain Microinstructions And Template Information

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US Patent:
6618801, Sep 9, 2003
Filed:
Feb 2, 2000
Appl. No.:
09/496845
Inventors:
Patrick Knebel - Ft Collins CO
Kevin David Safford - Fort Collins CO
Joel D Lamb - Ft Collins CO
Stephen R. Undy - Ft Collins CO
Russell C Brockmann - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1500
US Classification:
712215, 712211
Abstract:
The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Method And Apparatus For Verifying The Fine-Grained Correctness Of A Behavioral Model Of A Central Processor Unit

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US Patent:
6625759, Sep 23, 2003
Filed:
Feb 18, 2000
Appl. No.:
09/502366
Inventors:
Jeremy Petsinger - Fort Collins CO
Kevin David Safford - Fort Collins CO
Karl P. Brummel - Fort Collins CO
Russell C. Brockmann - Fort Collins CO
Bruce A. Long - Loveland CO
Patrick Knebel - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
H02H 305
US Classification:
714 28, 714 30, 714 34, 714 21
Abstract:
A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

Method And Apparatus For Testing Microarchitectural Features By Using Tests Written In Microcode

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US Patent:
6643800, Nov 4, 2003
Filed:
Feb 2, 2000
Appl. No.:
09/496367
Inventors:
Kevin David Safford - Fort Collins CO
Patrick Knebel - Ft Collins CO
Russell C Brockmann - Ft Collins CO
Karl P Brummel - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1100
US Classification:
714 35, 712227
Abstract:
An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

Methods And Apparatus For Exchanging The Contents Of Registers

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US Patent:
6668315, Dec 23, 2003
Filed:
Nov 26, 1999
Appl. No.:
09/449804
Inventors:
Kevin David Safford - Fort Collins CO
Patrick Knebel - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9455
US Classification:
712219, 712222, 712225, 703 26
Abstract:
A processor based computer system having dependency checking logic and a register stack, wherein the system overrides the dependency logic such that move instructions associated with the stack registers may be executed in parallel. The system operates such that it can be determined whether a stack underflow exception has occurred and if it has, the move instructions can be flushed, and a micro-code handler algorithm invoked that operates to allow execution of the move instructions in parallel without a stack underflow exception.

Method And Apparatus For Emulating An Instruction Set Extension In A Digital Computer System

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US Patent:
6681322, Jan 20, 2004
Filed:
Nov 26, 1999
Appl. No.:
09/449846
Inventors:
Kevin David Safford - Fort Collins CO
Patrick Knebel - Ft Collins CO
Assignee:
Hewlett-Packard Development Company L.P. - Houston TX
International Classification:
G06F 900
US Classification:
712244, 712218, 712215
Abstract:
Methods for emulating an instruction set extension, comprising providing data to be operated upon, executing a first instruction with respect to a first portion of the data without committing the results of the first executed instruction, if no unmasked exceptions occur with respect to the first portion of the data, executing a second instruction with respect to a second portion of the data, and if no unmasked exceptions occur with respect to the second portion of the data, committing the results of the second executed instruction and again executing the first instruction with respect to the first portion of the data. If the first instruction is executed again, its results are committed. A handler is invoked if an unmasked exception occurs.

Apparatus And Method For Conditionally Flushing A Pipeline Upon A Failure Of A Test Condition

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US Patent:
6745322, Jun 1, 2004
Filed:
Feb 18, 2000
Appl. No.:
09/507505
Inventors:
Russell C Brockmann - Ft Collins CO
Patrick Knebel - Ft Collins CO
Kevin David Safford - Fort Collins CO
Rohit Bhatia - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, LP. - Houston TX
International Classification:
G06F 944
US Classification:
712239
Abstract:
A method and apparatus that utilizes a simple test and flush mechanism to implement branch instructions of one Instruction Set Architecture (ISA) using instructions of another ISA is described. During the decoding and sequencing of microinstructions to implement a branch instruction, a fix-up address, which represents the remedial branch target in the event of a mispredicted target or branch condition, is determined and stored. A test condition is set to determine if the prediction or the branch condition was correct. When the test condition fails, the instruction execution pipeline is immediately flushed to avoid executing any instruction remaining in the pipeline following the branch instructions. The flushing of the pipeline signals the instruction fetch control mechanism to redirect the instruction flow to the instruction corresponding to the fix-up address. A method and apparatus according to the present invention further allows flushing of the pipeline when conditions other than ones involved in branch instructions occurs, e. g.

Method And Apparatus For Efficiently Generating, Storing, And Consuming Arithmetic Flags Between Producing And Consuming Macroinstructions When Emulating With Microinstructions

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US Patent:
6807625, Oct 19, 2004
Filed:
Feb 18, 2000
Appl. No.:
09/507032
Inventors:
Patrick Knebel - Ft Collins CO
Mark Gibson - Timnath CO
Rohit Bhatia - Fort Collins CO
Kevin David Safford - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1500
US Classification:
712221
Abstract:
An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.
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Patrick J Knebel from Fort Collins, CO, age ~60 Get Report