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Pete H Hudson

from Escondido, CA
Age ~83
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Also known as:
Peter H Hudson
Phone and address:
1653 Palomino Ln, Escondido, CA 92025
(760) 233-9924
Related to:
Mary Hudson, 76Marjorie Hudson, 82
Connected to:
Adela HudsonAja C HudsonAlaric P Hudson, 40Alec H Hudson, 64Allison R Hudson, 42Alora Hudson, 33Andrea Hudson, 51Antisha Hudson, 35Ashleigh R Hudson, 34Ashly F Hudson, 41

Pete Hudson Phones & Addresses

  • 1653 Palomino Ln, Escondido, CA 92025 (760) 233-9924 (760) 747-0501
  • 28683 Mountain Lilac Rd, Escondido, CA 92026 (760) 749-7653
  • San Diego, CA
  • 1653 Palomino Ln, Escondido, CA 92025

Resumes

Resumes

Pete Hudson Photo 1

Program Manager

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Location:
Tucson, AZ
Industry:
Electrical/Electronic Manufacturing
Work:
Pulse Engineering
Program Manager
Education:
Stanford University 1968 - 1971
Pete Hudson Photo 2

Pete Hudson

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Location:
San Diego, CA
Industry:
Electrical/Electronic Manufacturing
Work:
The University of Arizona
Education:
University of Arizona
Masters, Electronics Engineering
Pete Hudson Photo 3

Pete Hudson

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Pete Hudson Photo 4

Pete Hudson

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Pete H. Hudson
President
Ups 'n Downs Agility Club, Inc
1653 Palomino Ln, Escondido, CA 92025
1517 Melrose Ave, Chula Vista, CA 91911

Publications

Wikipedia

Peter Huds

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Peter John Hudson AM (born 1946) is a former Australian Rules Football player, considered one of the greatest full-forwards in the game's history. Hudson was ...

Us Patents

Chip Scale Packaging On Cte Matched Printed Wiring Boards

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US Patent:
6560108, May 6, 2003
Filed:
Feb 16, 2000
Appl. No.:
09/504637
Inventors:
Ching P. Lo - Rancho Palos Verdes CA
Daniel A. Huang - West Hills CA
Pete Hudson - Escondido CA
Assignee:
Hughes Electronics Corporation - El Segundo CA
International Classification:
H05K 720
US Classification:
361704, 361702, 257707, 174 163
Abstract:
A circuit assembly has a heat sink assembly and a chip scale package assembly. The chip scale package assembly has an integrated circuit die coupled to a first printed wiring board. The heat sink assembly has an integrated circuit die coupled to a second printed wiring board. Preferably, the heat sink assembly and the chip scale package assembly are assembled separately then assembled together. The circuit pads on the first printed wiring board correspond with circuit pads on the second printed wiring board. The circuit pads may be coupled together by solder or adhesive bonding. The circuit pads on the first printed wiring board may have solder balls formed of high temperature solder that do not melt when the heat sink assembly is assembled with chip scale package assembly. The solder balls allow chip scale package assembly to maintain a predetermined distance from the circuit pads on the second printed wiring board.

Chip Scale Packaging On Cte Matched Printed Wiring Boards

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US Patent:
6757968, Jul 6, 2004
Filed:
Aug 30, 2002
Appl. No.:
10/232273
Inventors:
Ching P. Lo - Rancho Palos Verdes CA
Daniel A. Huang - West Hills CA
Pete Hudson - Escondido CA
Assignee:
The Boeing Company - Chicago IL
International Classification:
H05K 334
US Classification:
29840, 29831, 29832, 29847, 29852, 361702, 361704, 361719, 257E2151, 257E23063, 174 163, 174260
Abstract:
A circuit assembly has a heat sink assembly and a chip scale package assembly. The chip scale package assembly has an integrated circuit die coupled to a first printed wiring board. The heat sink assembly has an integrated circuit die coupled to a second printed wiring board. Preferably, the heat sink assembly and the chip scale package assembly are assembled separately then assembled together. The circuit pads on the first printed wiring board correspond with circuit pads on the second printed wiring board. The circuit pads may be coupled together by solder or adhesive bonding. The circuit pads on the first printed wiring board may have solder balls formed of high temperature solder that do not melt when the heat sink assembly is assembled with chip scale package assembly. The solder balls allow chip scale package assembly to maintain a predetermined distance from the circuit pads on the second printed wiring board.

Chip Scale Package

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US Patent:
61093696, Aug 29, 2000
Filed:
Jan 29, 1999
Appl. No.:
9/239608
Inventors:
William Robert Crumly - Anaheim CA
Pete Henry Hudson - Escondido CA
Robert Joseph Cochrane - Riverside CA
Haim Feigenbaum - Irvine CA
Eric Dean Jensen - Irvine CA
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
H05K 2328
US Classification:
175 521
Abstract:
A chip scale package includes a mandrel built flexible circuit having a circuit trace on a first surface and an aperture extending therethrough. The chip scale package includes a pad covering the aperture on the first surface of the flexible circuit and a raised interconnection member extending outwardly from the pad. The chip scale package also includes a chip secured to a second surface of the flexible circuit, such that the chip is electrically connected to the pad.

Layer To Layer Interconnect

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US Patent:
60076690, Dec 28, 1999
Filed:
Jan 7, 1998
Appl. No.:
9/003651
Inventors:
William R. Crumly - Anaheim CA
Haim Feigenbaum - Irvine CA
Eric Dean Jensen - Irvine CA
Pete Henry Hudson - Escondido CA
John De Nuto - Warren OH
Assignee:
Packard Hughes Interconnect Company - Irvine CA
International Classification:
H05K 336
US Classification:
1563031
Abstract:
The present invention includes stack flexible circuit layers having raised features or bumps for Z-axis interconnection to another circuit layer or electrical component. An intermediate or adhesive layer separates each circuit layer. The multiple layers are stacked with the raised features from one layer aligning with pads of an overlying or underlying layer and are laminated so that the raised features pierce the intermediate or adhesive layer and make electrical contact with the corresponding pad of the adjacent circuit layer. The raised features may have a shape sufficient to penetrate the intermediate and/or the adhesive layer allowing blind vias to be made without pre-drilling the intermediate or adhesive layers. The intermediate layer of film can have a function other than or in addition to that of an adhesive. For example, in a connector application where the raised feature is used to make contact to corresponding pads, a film that has a low permeability to water could be placed between the raised features and corresponding pads on the next layer.
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Pete H Hudson from Escondido, CA, age ~83 Get Report