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Peter M Ippolito

from Austin, TX
Age ~66
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Also known as:
Pete Ippolito, Peter M Ippalito
Phone and address:
9205 Brigadoon Cv, Austin, TX 78750
(512) 219-0451
Related to:
Robert Brian Watt, 54Marilyn PulliamCollier S Cook, 49Marilyn Cook, 81Peter Cook, 66Irma Cook
Connected to:
Elena P Ippolito, 57Evan J Ippolito, 30Gayle E Ippolito, 55Melissa L Ippolito, 52Sergey P Ippolitov, 74Sara L Ipsa, 32George C Ipsarides, 58Lindsey Ipsen, 41Michael B Ipson, 44Ameena Iqbal, 39

Peter Ippolito Phones & Addresses

  • 9205 Brigadoon Cv, Austin, TX 78750 (512) 219-0451
  • Horseshoe Bay, TX
  • Llano, TX
  • Fishkill, NY
  • Wappingers Falls, NY

Industries

Semiconductors

Resumes

Resumes

Peter Ippolito Photo 1

Sr. Member Of Technical Staff, Intel Corporation

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Location:
Austin, Texas Area
Industry:
Semiconductors

Publications

Us Patents

Data Latch With Minimal Setup Time And Launch Delay

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US Patent:
7548102, Jun 16, 2009
Filed:
Jul 14, 2006
Appl. No.:
11/457668
Inventors:
Ambica Ashok - Austin TX, US
Cody B. Croxton - Austin TX, US
Peter M. Ippolito - Austin TX, US
Prashant U. Kenkare - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03K 3/289
US Classification:
327202, 327210, 327212, 326 95
Abstract:
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “implicit” pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an “explicit” pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.

Video Conferencing Apparatus For Group Video Conferencing

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US Patent:
60725222, Jun 6, 2000
Filed:
Jun 4, 1997
Appl. No.:
8/868798
Inventors:
Peter M. Ippolito - Austin TX
Caroline M. Cook - Austin TX
Assignee:
CGC Designs - Austin TX
International Classification:
H04N 714
US Classification:
348 15
Abstract:
A group video conferencing apparatus for the purposes of facilitating a video conference involving a group of participants which are azymuthly located about said apparatus is described. Means are are provided for the identification of a principle speaker and for the positioning of the video camera so as to capture the image of the principle speaker. Identification of the azymuthal orientation of the principle speaker is realized through the electronic processing of audio signals generated by the group of participants, and the azymuthal positioning of the video camera is adjusted through electromechanical means so as to capture the image of the identified principle speaker.

Combination Multiple Credit Card Holder And Money Clip

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US Patent:
57183295, Feb 17, 1998
Filed:
Jul 8, 1996
Appl. No.:
8/677669
Inventors:
Peter M. Ippolito - Austin TX
Caroline M. Cook - Austin TX
International Classification:
A45C 1118
US Classification:
206 38
Abstract:
A compartment is formed from the assembly of a bottom panel, a top panel, a right side panel, a left side panel, and a rear panel. The compartment is suitably sized so as to retain a multiple number of credit cards which are inserted into the compartment through a front opening and which are arranged inside the compartment in a stack and with a same physical orientation. The cards are securely retained inside the compartment by an integrated retention clip, and the cards are extracted from the compartment by means involving an integrated notch. A money clip affixed to the compartment provides a means for the retention of foldable paper currency.

Sense Circuit For On-Chip Thermal Shutdown

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US Patent:
52067785, Apr 27, 1993
Filed:
May 16, 1991
Appl. No.:
7/701490
Inventors:
Denis M. Flynn - San Jose CA
Peter M. Ippolito - Fishkill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H02H 504
US Classification:
361103
Abstract:
An on-chip thermal shutdown circuit senses the average junction temperature of an integrated circuit device. The on-chip circuit generates a signal when the junction temperature exceeds a preset limit. This signal may then be used to control other circuitry such that the electrical shutdown of the integrated circuit device is enabled under conditions of excessive device temperature. In this manner, catastrophic device damage can be avoided and the host system can be notified of the existence of a fault condition.

Laser Disk Holder With One Touch Disk Demounting

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US Patent:
58295828, Nov 3, 1998
Filed:
Mar 24, 1997
Appl. No.:
8/823511
Inventors:
Peter M. Ippolito - Austin TX
Caroline M. Cook - Austin TX
International Classification:
B65D 8557
US Classification:
2063081
Abstract:
A novel laser disk holder is described which permits the demounting of a laser disk that is mounted thereupon through the application of a simple one touch action. Demounting of the laser disk is achieved through the application of downward pushing force onto a center release button which has the effect of nullifying the interference fit which exists between the center opening of the laser disk and the center element onto which it is mounted upon. Resilient lifting arms then act to urge the demounted laser disk upwards and away from the top surface of the laser disk holder, thus making the laser disk available to be grasped by an individual.

High Performance Method For Reduction Of Memory Power Consumption Employing Ram Retention Mode Control With Low Latency And Maximum Granularity

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US Patent:
20190311748, Oct 10, 2019
Filed:
Apr 9, 2018
Appl. No.:
15/948251
Inventors:
- Austin TX, US
David A. Brown - Austin TX, US
Peter M. Ippolito - Austin TX, US
Ilhan Hatirnaz - Munich, DE
Assignee:
NXP USA, Inc. - Austin TX
International Classification:
G11C 5/14
Abstract:
A power control system, method, and architecture are disclosed for a multi-bank memory which provides independent, concurrent memory access to at least one memory block in each memory bank by using observation circuits to monitor bus masters connected over bus master interface signals to an interconnect for memory access requests to the multi-bank memory and to provide notifications to a power control circuitry that a valid memory access request was issued by a bus master over the bus master interface, where the power control circuitry processes the notifications received from each observation circuit and generates therefrom power control signals that are provided directly to each memory block and to bypass the interconnect, thereby separately controlling a power state for each memory block with power-up control signals that arrive at each memory block at or before a memory access request sent over the interconnect.
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Peter M Ippolito from Austin, TX, age ~66 Get Report