Resumes
Resumes
Mts Silicon Design Engineer
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Amd
Mts Silicon Design Engineer
Atomic Feb 2018 - Mar 2019
Rtl Engineer
Rex Computing Nov 1, 2015 - Feb 2018
Rtl Engineer
Scalable Systems Research Labs Inc. Jun 2015 - Nov 2015
Asic Design Engineer
Pmc-Sierra Sep 2014 - May 2015
Esd Nsg Applications Engineer Coop
Mts Silicon Design Engineer
Atomic Feb 2018 - Mar 2019
Rtl Engineer
Rex Computing Nov 1, 2015 - Feb 2018
Rtl Engineer
Scalable Systems Research Labs Inc. Jun 2015 - Nov 2015
Asic Design Engineer
Pmc-Sierra Sep 2014 - May 2015
Esd Nsg Applications Engineer Coop
Education:
San Jose State University 2013 - 2015
Master of Science, Masters, Electrical Engineering, Vlsi Design University of Mumbai 2008 - 2012
Bachelor of Engineering, Bachelors, Engineering, Electronics
Master of Science, Masters, Electrical Engineering, Vlsi Design University of Mumbai 2008 - 2012
Bachelor of Engineering, Bachelors, Engineering, Electronics
Skills:
Verilog
Asic
C++
C
Systemverilog
Vlsi
Rtl Design
Perl
Static Timing Analysis
Fpga
Matlab
Soc
Rtl Verification
Xilinx Ise
Modelsim
Logic Design
Timing
Linux
Tcl
Logic Synthesis
Xilinx
Synopsys Tools
Debugging
Python
Altera Quartus
Simulations
Application Specific Integrated Circuits
Photography
Field Programmable Gate Arrays
Synopsys Primetime
Flash Memory
Cache Coherency
Fifo
Freebsd
System on A Chip
Very Large Scale Integration
Computer Architecture
Cadence Encounter
Microarchitecture
Chip Architecture
Formal Verification
Universal Verification Methodology
Asic
C++
C
Systemverilog
Vlsi
Rtl Design
Perl
Static Timing Analysis
Fpga
Matlab
Soc
Rtl Verification
Xilinx Ise
Modelsim
Logic Design
Timing
Linux
Tcl
Logic Synthesis
Xilinx
Synopsys Tools
Debugging
Python
Altera Quartus
Simulations
Application Specific Integrated Circuits
Photography
Field Programmable Gate Arrays
Synopsys Primetime
Flash Memory
Cache Coherency
Fifo
Freebsd
System on A Chip
Very Large Scale Integration
Computer Architecture
Cadence Encounter
Microarchitecture
Chip Architecture
Formal Verification
Universal Verification Methodology
Interests:
Environment
Languages:
English
Hindi
Marathi
Hindi
Marathi