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Richard E Demaray

from Portola Valley, CA
Age ~78
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Also known as:
Richard Ernest Demaray, Ernest Demaray
Phone and address:
190 Fawn Ln, Menlo Park, CA 94028
(650) 529-9027
Related to:
Barbara G Nelson, 53Katherine Demaray, 32Jason D Nelson, 42Melissa DemaraySharilyn NelsonGwen NelsenHeather Haberman, 54
Connected to:
Amy M Demaray, 38Cathleen G Demaray, 45Holly J Demaray, 47Kathleen D Demaray, 71Blair G Demarco, 60Brian R Demarco, 47Charles J Demarco, 76Ernesto C DemarcoGlen M Demarco, 68Heidi E Demarco, 65

Richard Demaray Phones & Addresses

  • 190 Fawn Ln, Portola Valley, CA 94028 (650) 529-9027 (650) 851-5467
  • Portola Vally, CA
  • New Orleans, LA
  • San Marino, CA
  • 5006 Crystal Ridge Ct, Oakland, CA 94605 (510) 799-1679
  • 1050 Canterbury, Hercules, CA 94547 (510) 799-1679
  • 1051 Canterbury, Hercules, CA 94547
  • Portola Vally, CA

Publications

Us Patents

Collimated Sputtering Of Semiconductor And Other Films

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US Patent:
6362097, Mar 26, 2002
Filed:
Jul 14, 1998
Appl. No.:
09/115258
Inventors:
Richard Ernest Demaray - Portola Valley CA
Chandra Deshpandey - Fremont CA
Rajiv Gopal Pethe - Sunnyvale CA
Assignee:
Applied Komatsu Technlology, Inc. - Tokyo
International Classification:
H01L 2144
US Classification:
438674, 438792
Abstract:
Thin semiconductor films or layers having a pre-selected degree of crystallinity, from amorphous material to poly-crystalline material, can be obtained by selecting an appropriate aspect ratio for a collimator used during a sputtering process. The orientation of the deposited film also can be tailored by selection of the collimator aspect ratio. Sputtered collimation permits highly crystalline films to be formed at temperatures significantly below the annealing temperature of the sputtered material. Thus, required fabrication steps and increase the throughput of the use of low temperatures allows films of substantially greater crystallinity and carrier mobility to be fabricated on glass and other low temperature substrates. Additionally, thin semiconductor Trapped charge defects also can be reduced by grounding the collimator to provide electrical isolation between the charged plasma particles and the substrate on which the sputtered layer is to be formed. Dielectric films having a thickness as small as several hundred can be formed to fabricate high transconductance devices with high breakdown strengths.

Electrically Insulating Sealing Structure And Its Method Of Use In A Semiconductor Manufacturing Apparatus

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US Patent:
6436509, Aug 20, 2002
Filed:
Jan 6, 2000
Appl. No.:
09/478940
Inventors:
Richard Ernest Demaray - Portola Valley CA
Manuel J. Herrera - San Mateo CA
David F. Eline - Menlo Park CA
Chandra Deshpandey - Fremont CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
428141, 428414, 428413, 428416, 2642724, 26427217, 20425812, 20425815, 20425807, 156330, 118733
Abstract:
In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10 Torr, and which can function at a continuous operating temperature of about 300Â F. (148. 9Â C. ) or greater. The insulating sealing structure may be fabricated solely from particular polymeric materials or may comprise a center reinforcing member having at least one layer applied to its exterior surface, where the at least one surface layer provides at least a portion of the insulating properties and provides the surface finish necessary to make an adequate seal with a mating surface.

Planar Optical Devices And Methods For Their Manufacture

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US Patent:
6506289, Jan 14, 2003
Filed:
Jul 10, 2001
Appl. No.:
09/903050
Inventors:
Richard E. Demaray - Portola Valley CA
Kai-An Wang - Cupertino CA
Ravi B. Mullapudi - San Jose CA
Douglas P. Stadtler - Morgan Hill CA
Hongmei Zhang - San Jose CA
Rajiv Pethe - San Jose CA
Assignee:
Symmorphix, Inc. - Sunnyvale CA
International Classification:
C23C 1434
US Classification:
20419226, 20419212, 20419215, 20419222, 20419223
Abstract:
Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.

Method Of Producing Amorphous Silicon For Hard Mask And Waveguide Applications

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US Patent:
6533907, Mar 18, 2003
Filed:
Jan 19, 2001
Appl. No.:
09/766463
Inventors:
Richard E. Demaray - Portola Valley CA
Jesse Shan - San Jose CA
Kai-An Wang - Cupertino CA
Ravi B. Mullapudi - San Jose CA
Assignee:
Symmorphix, Inc. - Sunnyvale CA
International Classification:
C23C 1434
US Classification:
20419225, 20419212
Abstract:
A specialized physical vapor deposition process provides dense amorphous semiconducting material with exceptionally smooth morphology. In particular, the process provides dense, smooth amorphous silicon useful as a hard mask for etching optical and semiconductor devices and as a high refractive index material in optical devices. DC sputtering of a planar target of intrinsic crystalline semiconducting material in the presence of a sputtering gas under a condition of uniform target erosion is used to deposit amorphous semiconducting material on a substrate. DC power that is modulated by AC power is applied to the target. The process provides dense, smooth amorphous silicon at high deposition rates. A method of patterning a material layer including forming a hard mask layer of amorphous silicon on a material layer according to the present DC sputtering process is also provided. The low average surface roughness of the amorphous silicon hard mask is reflected in the low average surface roughness of the sidewalls of the etched material layer.

Shadow Frame For Substrate Processing

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US Patent:
6773562, Aug 10, 2004
Filed:
Feb 20, 1998
Appl. No.:
09/026575
Inventors:
Makoto Inagawa - Menlo Park CA
Akihiro Hosokawa - Cupertino CA
Richard E. Demaray - Portola Valley CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1434
US Classification:
20429815, 15634551, 118728, 118500, 118503
Abstract:
A vacuum processing chamber with walls defining a cavity for processing a substrate. The processing chamber includes a substrate support for supporting a substrate being processed in the cavity, a shadow frame for preventing processing of a perimeter portion of the substrate, and a shadow frame support supporting the shadow frame within the cavity. The shadow frame is positionable with a gap between an underside of the shadow frame and an upper surface of the substrate. At least one conductive element insulated from the walls and establishes a conductive path from the shadow frame to outside the cavity. The conductive path may be used to discharge charge from the shadow frame at a rate sufficient to prevent a voltage differential from accumulating between the shadow frame and the substrate which would cause arcing therebetween, or to apply a bias voltage to the shadow frame sufficient to attract particles to reduce contamination of the substrate.

Method Of Forming An Electrically Insulating Sealing Structure For Use In A Semiconductor Manufacturing Apparatus

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US Patent:
6821562, Nov 23, 2004
Filed:
Jun 25, 2002
Appl. No.:
10/180436
Inventors:
Richard Ernest Demaray - Portola Valley CA
Manuel J. Herrera - San Mateo CA
David F. Eline - Menlo Park CA
Chandra Deshpandey - Fremont CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23C 1600
US Classification:
4272481, 4272554, 20419222, 20419223
Abstract:
In accordance with the present invention, an insulating sealing structure useful in physical vapor deposition apparatus is provided. The insulating sealing structure is capable of functioning under high vacuum and high temperature conditions. The apparatus is a three dimensional structure having a specifically defined range of electrical, chemical, mechanical and thermal properties enabling the structure to function adequately as an insulator which does not break down at voltages ranging between about 1,500 V and about 3,000 V, which provides a seal against a vacuum of at least about 10 Torr, and which can function at a continuous operating temperature of about 300Â F. (148. 9Â C. ) or greater. The insulating sealing structure may be fabricated solely from particular polymeric materials or may comprise a center reinforcing member having at least one layer applied to its exterior surface, where the at least one surface layer provides at least a portion of the insulating properties and provides the surface finish necessary to make an adequate seal with a mating surface. A first preferred embodiment comprises an aluminum center reinforcing member having at least one layer of a polymeric insulator applied to provide an insulating, sealing surface.

Planar Optical Devices And Methods For Their Manufacture

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US Patent:
6827826, Dec 7, 2004
Filed:
Nov 4, 2002
Appl. No.:
10/288278
Inventors:
Richard E. Demaray - Portola Valley CA
Kai-An Wang - Cupertino CA
Ravi B. Mullapudi - San Jose CA
Douglas P. Stadtler - Morgan Hill CA
Hongmei Zhang - San Jose CA
Rajiv Pethe - San Jose CA
Assignee:
Symmorphix, Inc. - Sunnyvale CA
International Classification:
C23C 1434
US Classification:
20419215, 20419212, 427452, 427453, 156 60
Abstract:
Physical vapor deposition processes provide optical materials with controlled and uniform refractive index that meet the requirements for active and passive planar optical devices. All processes use radio frequency (RF) sputtering with a wide area target, larger in area than the substrate on which material is deposited, and uniform plasma conditions which provide uniform target erosion. In addition, a second RF frequency can be applied to the sputtering target and RF power can be applied to the substrate producing substrate bias. Multiple approaches for controlling refractive index are provided. The present RF sputtering methods for material deposition and refractive index control are combined with processes commonly used in semiconductor fabrication to produce planar optical devices such surface ridge devices, buried ridge devices and buried trench devices. A method for forming composite wide area targets from multiple tiles is also provided.

Mode Size Converter For A Planar Waveguide

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US Patent:
6884327, Apr 26, 2005
Filed:
Mar 16, 2002
Appl. No.:
10/101492
Inventors:
Tao Pan - San Jose CA, US
Richard E. Demaray - Portola Valley CA, US
Yu Chen - San Jose CA, US
Yong Jin Xie - Cupertino CA, US
Rajiv Pethe - San Jose CA, US
International Classification:
C23C014/34
US Classification:
20419212, 4272481, 427259, 427282
Abstract:
A process for forming a mode size converter with an out-of-plane taper formed during deposition with a shadow mask is disclosed. Mode-size converters according to the present invention can have any number of configurations. Measured coupling efficiencies for waveguides with mode size converters according to the present invention show marked improvement.
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Richard E Demaray from Portola Valley, CA, age ~78 Get Report