Resumes
Resumes
Richard Glackemeyer Phones & Addresses
-
Hull, MA
-
11 Oak St, Wellesley, MA 02482 (781) 237-5742 (781) 237-5761
-
Harvard, MA
-
Concord, MA
Publications
Us Patents
Method And Apparatus For Isolating Faults In A Digital Logic Circuit
View pageUS Patent:
47275456, Feb 23, 1988
Filed:
Sep 2, 1986
Appl. No.:
6/902614
Inventors:
Richard E. Glackemeyer - Harvard MA
Robert C. Petty - Princeton MA
Calvin F. Page - Brookline NH
Robert C. Petty - Princeton MA
Calvin F. Page - Brookline NH
Assignee:
Digital Equipment Corporation - Worcester MA
International Classification:
G06F 1100
US Classification:
371 23
Abstract:
The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for execution by a service processor of the actual computer during testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnostic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit elements not capable of generating such fault indications.
Instruction Prefetch System For Conditional Branch Instruction For Central Processor Unit
View pageUS Patent:
47424516, May 3, 1988
Filed:
May 21, 1984
Appl. No.:
6/612621
Inventors:
William F. Bruckert - Hudson MA
Tryggve Fossum - Northboro MA
John A. DeRosa - Princeton MA
Richard E. Glackemeyer - Bolton MA
Allan E. Helenius - Westford MA
John C. Manton - Marlboro MA
Tryggve Fossum - Northboro MA
John A. DeRosa - Princeton MA
Richard E. Glackemeyer - Bolton MA
Allan E. Helenius - Westford MA
John C. Manton - Marlboro MA
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 942
US Classification:
364200
Abstract:
A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has separate portions, one that retrieves operands and the other that retrieves instructions. When the fetch unit fetches a conditional branch instruction, it may continue to prefetch "branch not taken" instructions using the instruction fetch portion. The fetch unit initially uses the operand fetch portion to prefetch "branch taken" instructions. If it is determined that the branch is not taken, the prefetch operation is aborted, otherwise the prefetch operation is allowed to continue to provide the next instruction used by the processor.