Search

Robert F Netting

from Portland, OR
Age ~60
Get Report
Also known as:
Robert Frazier Netting, Robert Frazier Benficiary Netting, Robert Frazier Netting Beneficiary, Robert F Trs, Bob Netting, Rob Netting, Robert Netting Frazier
Phone and address:
1555 116Th Ave, Portland, OR 97229
(503) 643-8131
Connected to:
David A Nettle, 56Adam Nettlefold, 40Aaron J Nettles, 51Bill NettlesCharlie E Nettles, 63Christa N Nettles, 44Christian D Nettles, 48Darin Nettles, 58Debbie A Nettles, 73Dennis J Nettles, 64

Robert Netting Phones & Addresses

  • 1555 116Th Ave, Portland, OR 97229 (503) 643-8131
  • Tucson, AZ
  • Hillsboro, OR
  • Folsom, CA
  • Tempe, AZ
  • Chandler, AZ

Work

Company: Intel corporation Jul 1985 to Apr 2013 Position: Principal engineer

Education

School / High School: Stanford University 1981 to 1985

Skills

Microarchitecture

Industries

Computer Hardware

Resumes

Resumes

Robert Netting Photo 1

Robert Netting

View page
Location:
Portland, OR
Industry:
Computer Hardware
Work:
Intel Corporation Jul 1985 - Apr 2013
Principal Engineer
Education:
Stanford University 1981 - 1985
Skills:
Microarchitecture

Publications

Isbn (Books And Publications)

Smallholders, Householders: Farm Families and the Ecology of Intensive, Sustainable Agriculture

View page
Author

Robert McC Netting

ISBN #

0804721025

Balancing on an Alp: Ecological Change and Continuity in a Swiss Mountain Community

View page
Author

Robert M. Netting

ISBN #

0521237432

Balancing on an Alp: Ecological Change and Continuity in a Swiss Mountain Community

View page
Author

Robert M. Netting

ISBN #

0521281970

Smallholders, Householders: Farm Families and the Ecology of Intensive, Sustainable Agriculture

View page
Author

Robert M. Netting

ISBN #

0804720614

Cultural Ecology

View page
Author

Robert M. Netting

ISBN #

0846548402

Cultural Ecology

View page
Author

Robert M. Netting

ISBN #

0881332046

Households: Comparative and Historical Studies of the Domestic Group

View page
Author

Robert Netting

ISBN #

0520049969

Households: Comparative and Historical Studies of the Domestic Group

View page
Author

Robert Netting

ISBN #

0520049977

Us Patents

Method And Apparatus For Limiting Processor Clock Frequency

View page
US Patent:
6633993, Oct 14, 2003
Filed:
Jan 22, 2002
Appl. No.:
10/051051
Inventors:
James A. Wilson - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Method And Apparatus For Limiting Processor Clock Frequency

View page
US Patent:
7134037, Nov 7, 2006
Filed:
Aug 13, 2003
Appl. No.:
10/640752
Inventors:
James A. Wilson - Portland OR, US
Robert F. Netting - Portland OR, US
Peter Des Rosier - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/04
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Method And Apparatus For Limiting Processor Clock Frequency

View page
US Patent:
7395449, Jul 1, 2008
Filed:
Nov 6, 2006
Appl. No.:
11/593889
Inventors:
James A. Wilson - Portland OR, US
Robert F. Netting - Portland OR, US
Peter Des Rosier - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/04
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Boot Strap Processor Assignment For A Multi-Core Processing Unit

View page
US Patent:
20140006767, Jan 2, 2014
Filed:
Dec 29, 2011
Appl. No.:
13/993310
Inventors:
Steven S. Chang - San Jose CA, US
Anshuman Thakur - Beaverton OR, US
Ramacharan Charan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US
Jay S. Lawlor - Hillsboro OR, US
Robert F. Netting - Hillsboro OR, US
International Classification:
G06F 9/44
US Classification:
713 2
Abstract:
Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

Method And Apparatus For Limiting Processor Clock Frequency

View page
US Patent:
6385735, May 7, 2002
Filed:
Dec 15, 1997
Appl. No.:
08/990526
Inventors:
James A. Wilson - Portland OR
Robert F. Netting - Portland OR
Peter Des Rosier - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 104
US Classification:
713501, 713601
Abstract:
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. A comparator circuit compares a selected processor clock frequency to the maximum processor clock frequency to determine if the selected processor clock frequency is permitted. If the selected processor clock frequency is not permitted, then the processor is not allowed to operate at the selected clock frequency.

Advanced Programmable Interrupt Controller Identifier (Apic Id) Assignment For A Multi-Core Processing Unit

View page
US Patent:
20140156896, Jun 5, 2014
Filed:
Dec 29, 2011
Appl. No.:
13/994104
Inventors:
Steven S. Chang - San Jose CA, US
Anshuman Thakur - Beaverton OR, US
Ramacharan Sundararaman - Hillsboro OR, US
Ramon Matas - Portland OR, US
Jay S. Lawlor - Hillsboro OR, US
Robert F. Netting - Hillsboro OR, US
International Classification:
G06F 13/24
US Classification:
710267
Abstract:
Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique advanced programmable interrupt controller (APIC) identifier (ID). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned an APIC ID or as ineligible to be assigned the APIC ID.
Control profile
Robert F Netting from Portland, OR, age ~60 Get Report