Search

Roy G Musselman

from Rochester, MN
Age ~67
Get Report
Also known as:
Roy G Mosselman
Phone and address:
5106 Castlewood Ln NW, Rochester, MN 55901
(507) 281-9565
Related to:
Edward R Musselman, 70Megan E Musselman, 37Linden C Potts, 40Maureen C Musselman, 66Laura B Musselman, 34Lisa J Musselman, 37
Connected to:
Eric Musselman, 43Frank T Mussell, 80James B Mussell, 57John W Mussell, 76Judy A Musselman, 62Julie L Musselman, 83Kati R Musselman, 37Kelly A Musselman, 60Leslie A Musselmann, 54Lori K Musselman, 53

Roy Musselman Phones & Addresses

  • 5106 Castlewood Ln NW, Rochester, MN 55901 (507) 281-9565
  • Apalachin, NY
  • Eau Claire, WI
  • 5106 Castlewood Ln NW, Rochester, MN 55901

Work

Company: Ibm Oct 2013 Position: Senior hpc application analyst

Education

Degree: Masters School / High School: University of Minnesota 2000 to 2005 Specialities: Computer Science

Skills

Linux • C++ • Bash • Test Planning • Test Automation • Regression Testing • Performance Measurement • Performance Analysis • Performance Tuning • Application Optimisation • User Acceptance Testing • Parallel Computing • Mpi • Supercomputing • High Performance Computing • Simulation Software • Functional Verification • Emulation • Palladium • Agile Methodolgy • Rational Team Concert • Requirements Gathering • Microsoft Office • Windows 7 • Openstack • Virtualization • Virtual Appliances • Vmware • Vsphere • Hyper V • Db2 • Drafting Patent Applications • Team Leadership • Distributed Team Management • Collaborative Problem Solving • Jenkins • Shell Scripting • Unix • Scalability

Industries

Computer Software

Resumes

Resumes

Roy Musselman Photo 1

Senior Hpc Application Analyst

View page
Location:
Rochester, MN
Industry:
Computer Software
Work:
Ibm
Senior Hpc Application Analyst
Ibm Jan 2005 - Jul 2013
Senior Software Engineer
Ibm Jan 1996 - Dec 2004
Advisory Hardware Engineer
Ibm Jun 1980 - Dec 1995
Staff Hardware Engineer
Education:
University of Minnesota 2000 - 2005
Masters, Computer Science Iowa State University 1975 - 1980
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Linux
C++
Bash
Test Planning
Test Automation
Regression Testing
Performance Measurement
Performance Analysis
Performance Tuning
Application Optimisation
User Acceptance Testing
Parallel Computing
Mpi
Supercomputing
High Performance Computing
Simulation Software
Functional Verification
Emulation
Palladium
Agile Methodolgy
Rational Team Concert
Requirements Gathering
Microsoft Office
Windows 7
Openstack
Virtualization
Virtual Appliances
Vmware
Vsphere
Hyper V
Db2
Drafting Patent Applications
Team Leadership
Distributed Team Management
Collaborative Problem Solving
Jenkins
Shell Scripting
Unix
Scalability

Publications

Us Patents

Method And Apparatus For Correlating Trace Data From Asynchronous Emulation Machines

View page
US Patent:
6556936, Apr 29, 2003
Filed:
Dec 27, 2000
Appl. No.:
09/748981
Inventors:
Thomas Michael Gooding - Rochester MN
Roy Glenn Musselman - Rochester MN
Robert Neill Newshutz - Rochester MN
Jeffery Joseph Ruedinger - Rochester MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1900
US Classification:
702115, 702179, 702182, 702183, 714 25
Abstract:
A method and apparatus are provided for correlating trace data from asynchronous machines, such as asynchronous emulation machines. A data capture signal is received from each of the plurality of asynchronous machines. The data capture signal from each of the plurality of asynchronous machines is sampled. Then the sampled data capture signal from each of the plurality of asynchronous machines and a cycle count are stored. A trace synchronization system is coupled to each of the plurality of asynchronous machines for receiving the data capture signal from each of the plurality of asynchronous machines. The trace synchronization system operates no slower than the data capture signal from each of the plurality of asynchronous machines, so that no data capture signals are missed.

Non-Synchronous Hardware Emulator

View page
US Patent:
6832185, Dec 14, 2004
Filed:
Mar 9, 2000
Appl. No.:
09/522354
Inventors:
Roy Glenn Musselman - Rochester MN
Jeffrey Joseph Ruedinger - Rochester MN
Assignee:
Quickturn Design Systems, Inc. - San Jose CA
International Classification:
G06F 9455
US Classification:
703 23
Abstract:
A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches. The hardware emulator described herein may thus be viewed as a hybrid of the FPGA type emulator and the time-multiplexed processor array emulator.

Time-Multiplexing Data Between Asynchronous Clock Domains Within Cycle Simulation And Emulation Environments

View page
US Patent:
6842728, Jan 11, 2005
Filed:
Mar 12, 2001
Appl. No.:
09/804210
Inventors:
Thomas Michael Gooding - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Robert N Newshutz - Rochester MN, US
Jeffrey Joseph Ruedinger - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9455
US Classification:
703 23, 702125, 703 16, 703 19, 703 20, 703 25, 703 27, 712 29, 712 35, 712203, 712206, 712223, 712245, 713400, 716 6, 716 16
Abstract:
An apparatus and method utilize a buffer interposed in a common signal path between asynchronous clock domains in a hardware-based logic emulation environment to manage the communication of time-multiplexed data signals between the clock domains during hardware-based emulation. The buffer is effectively used to latch each data signal communicated across the common signal path so that the clock domain that receives the signals can retrieve each such signal at appropriate points in the receiver clock domain's evaluation cycle. Independently-controlled write/read pointers are maintained in a buffer control circuit to independently address the buffer for the transmitter and receiver sides of an asynchronous communication path. Locations in the buffer are associated with specific steps in the evaluation cycles of each of the transmitter and receiver clock domains, and the write/read pointers are managed to respectively write and read data to and from the locations in the buffer based upon the current evaluation steps being performed within the respective evaluation cycles of the transmitter and receiver clock domains.

Method And Apparatus For The Automatic Correction Of Faulty Wires In A Logic Simulation Hardware Emulator / Accelerator

View page
US Patent:
7337103, Feb 26, 2008
Filed:
Jan 15, 2004
Appl. No.:
10/757788
Inventors:
Thomas Michael Gooding - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
US Classification:
703 23, 703 14, 714 25
Abstract:
The present invention provides a method, apparatus and program-product for a self-healing, reconfigurable logic emulation system, wherein if a signal wire becomes faulty in an emulation cable during an emulation run, the runtime software can automatically reconfigure the emulator to reroute the data destined for the faulty signal wire across a spare wire. Such a feature enables a user to restart the emulation run without having to recompile the simulation model to account for the hardware fault.

Method And Apparatus To Provide Alternative Stimulus To Signals Internal To A Model Actively Running On A Logic Simulation Hardware Emulator

View page
US Patent:
7437282, Oct 14, 2008
Filed:
Sep 22, 2005
Appl. No.:
11/232765
Inventors:
Roy Glenn Musselman - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
G06F 9/445
G06F 11/30
US Classification:
703 24, 703 27, 714738, 710 29
Abstract:
The present invention enhances the Direct Access Stimulus (DAS) interface presently employed within a logic simulation hardware emulator to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator. The present invention accomplishes this by introducing a set of special logic within the logic model to provide an alternate source for selected signals, identifies the special logic so that it is subsequently connected directly to the DAS card interface, and adds information to a symbol table so that this special logic can be identified as signal accessible through the DAS card interface. At runtime, when the user control program accesses facilities that have been connected to the DAS card interface, a set of special routines automatically reference the symbol table information to access the special logic that is connected to the DAS card interface.

Method And Apparatus To Increase The Usable Memory Capacity Of A Logic Simulation Hardware Emulator/Accelerator

View page
US Patent:
7480611, Jan 20, 2009
Filed:
May 13, 2004
Appl. No.:
10/845496
Inventors:
Thomas Michael Gooding - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/455
US Classification:
703 25, 703 27, 710 2
Abstract:
A method, apparatus and program product are provided for increasing the usable memory capacity of a logic simulation hardware emulator. The present invention performs an additional logic synthesis operation during model build to transform an original logical array within a logic model into a transformed logical array, such that a row within the transformed logical array includes a plurality of merged logical array rows from the original logical array. The invention further modifies read and write port logic surrounding the transformed logical array during the logic synthesis operation to support read and write accesses during model emulation run time.

Method And Apparatus For Routing Data In An Inter-Nodal Communications Lattice Of A Massively Parallel Computer System By Dynamically Adjusting Local Routing Strategies

View page
US Patent:
7680048, Mar 16, 2010
Filed:
Oct 6, 2006
Appl. No.:
11/539329
Inventors:
Charles Jens Archer - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Amanda Peters - Rochester MN, US
Kurt Walter Pinnow - Rochester MN, US
Brent Allen Swartz - Chippewa Falls WI, US
Brian Paul Wallenfelt - Eden Prairie MN, US
Assignee:
International Business Machiens Corporation - Armonk NY
International Classification:
G01R 31/08
G06F 11/00
H04L 12/28
H04L 12/56
US Classification:
370235, 370400
Abstract:
A massively parallel computer system contains an inter-nodal communications network of node-to-node links. Each node implements a respective routing strategy for routing data through the network, the routing strategies not necessarily being the same in every node. The routing strategies implemented in the nodes are dynamically adjusted during application execution to shift network workload as required. Preferably, adjustment of routing policies in selective nodes is performed at synchronization points. The network may be dynamically monitored, and routing strategies adjusted according to detected network conditions.

Method And Apparatus For Routing Data In An Inter-Nodal Communications Lattice Of A Massively Parallel Computer System By Employing Bandwidth Shells At Areas Of Overutilization

View page
US Patent:
7706275, Apr 27, 2010
Filed:
Feb 7, 2007
Appl. No.:
11/672315
Inventors:
Charles Jens Archer - Rochester MN, US
Roy Glenn Musselman - Rochester MN, US
Amanda Peters - Rochester MN, US
Kurt Walter Pinnow - Rochester MN, US
Brent Allen Swartz - Chippewa Falls WI, US
Brian Paul Wallenfelt - Eden Prairie MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/08
US Classification:
370235, 370389, 709240
Abstract:
A massively parallel computer system contains an inter-nodal communications network of node-to-node links. An automated routing strategy routes packets through one or more intermediate nodes of the network to reach a final destination. The default routing strategy is altered responsive to detection of overutilization of a particular path of one or more links, and at least some traffic is re-routed by distributing the traffic among multiple paths (which may include the default path). An alternative path may require a greater number of link traversals to reach the destination node.
Control profile
Roy G Musselman from Rochester, MN, age ~67 Get Report