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Ryan Justin Pennington

from Pflugerville, TX
Age ~44
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Also known as:
Ryan J Pennington, Ryan S Pennington, Maria Pennington, Maria Gonzales
Phone and address:
1611 Old Tract Rd, Pflugerville, TX 78660
(512) 989-2428
Related to:
Minnie L Pickard, 97Gabriel Gonzales, 45Sophia G Morris, 44Raul GonzalesReynaldo Belmares, 63
Connected to:
Alonzo Pennington, 44Bryan K Pennington, 56Brynne M Pennington, 43Dagnija A Pennington, 80Danielle N Pennington, 46Dann C Pennington, 79Denis L Penning, 55Denis W Pennington, 58Edwina L Pennington, 71Hunter C Pennington, 30

Ryan Pennington Phones & Addresses

  • 1611 Old Tract Rd, Pflugerville, TX 78660 (512) 989-2428
  • 2450 Wickersham Ln, Austin, TX 78741 (512) 447-5110
  • 2200 Pleasant Valley Rd, Austin, TX 78741 (512) 493-7015
  • Poplar Bluff, MO
  • Grand Rapids, MI
  • Fort Hood, TX
  • Travis, TX
  • 1611 Old Tract Rd, Pflugerville, TX 78660

Work

Position: Homemaker

Education

Degree: Associate degree or higher

Resumes

Resumes

Ryan Pennington Photo 1

Ryan Pennington

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Location:
Austin, TX
Industry:
Wireless
Work:
IBM - Austin, TX Aug 2012 - Jul 2013
Sr. Engineering Manager - Hardware Validation
IBM Jan 2012 - Sep 2012
Senior Engineer Silicon Validation
IBM Dec 2002 - Dec 2011
Product Engineer
Education:
Southern Illinois University, Carbondale 1997 - 2002
B.S., Electrical Engineering
Skills:
Simulations
Debugging
Dft
Silicon Validation
Failure Analysis
Microprocessors
Hardware Architecture
Perl
Project Management
Data Analysis
Processors
Computer Architecture
System Testing
Characterization
Software Development
Functional Verification
Vlsi
Hardware Testing
Stuff
Soc
Giant Robots
Yield Management
Product Engineering
Java
Cmos
Manufacturing Engineering
Reliability Engineering
Squirrel
Hardware Development
Sql
Engineering Management
Testing
Machine Learning
Research
Cryptocurrency
Vendoe
Ryan Pennington Photo 2

Ryan Pennington

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Ryan Pennington Photo 3

Ryan Pennington

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Location:
Pflugerville, TX
Ryan Pennington Photo 4

Ryan Pennington

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Ryan Pennington

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Ryan Pennington

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Ryan Pennington

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Publications

Us Patents

Method For Cache Correction Using Functional Tests Translated To Fuse Repair

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US Patent:
7770067, Aug 3, 2010
Filed:
Dec 1, 2008
Appl. No.:
12/325272
Inventors:
Walter R. Lockwood - Round Rock TX, US
Ryan J. Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth L. Wright - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 30
Abstract:
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Non-Disruptive Hardware Change

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US Patent:
8650431, Feb 11, 2014
Filed:
Aug 24, 2010
Appl. No.:
12/862492
Inventors:
Michael S. Floyd - Cedar Park TX, US
Ryan J. Pennington - Austin TX, US
Harmony L. Prince - Austin TX, US
Kevin F. Reick - Round Rock TX, US
David D. Sanner - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 3
Abstract:
A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.

Method For Cache Correction Using Functional Tests Translated To Fuse Repair

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US Patent:
20070101194, May 3, 2007
Filed:
Oct 27, 2005
Appl. No.:
11/260562
Inventors:
Walter Lockwood - Round Rock TX, US
Ryan Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth Wright - Austin US, US
International Classification:
G06F 11/00
US Classification:
714030000
Abstract:
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Method For Cache Correction Using Functional Tests Translated To Fuse Repair

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US Patent:
20090006916, Jan 1, 2009
Filed:
Sep 9, 2008
Appl. No.:
12/207496
Inventors:
Walter R. Lockwood - Round Rock TX, US
Ryan J. Pennington - Austin TX, US
Hugh Shen - Austin TX, US
Kenneth L. Wright - Austin TX, US
International Classification:
G06F 11/26
US Classification:
714733, 714E11159
Abstract:
A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect in the cache memory using the fault data, and repairing the defect by setting a fuse to reroute access requests for the location to a redundant array. The fault data may include an error syndrome and a failing address. The functional test procedure creates random cache access sequences that cause varying loads of traffic in the cache memory using a test pattern based on a random seed. The functional test procedure may be carried out after completion of a nonfunctional, built-in self test of the microprocessor which sets some of the fuses.

Host-Side Support Of Dynamically Changing Frequency In Memory Systems

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US Patent:
20130262791, Oct 3, 2013
Filed:
Mar 27, 2012
Appl. No.:
13/430807
Inventors:
Joab D. Henderson - Pflugerville TX, US
Ryan J. Pennington - Austin TX, US
Anuwat Saetow - Austin TX, US
Robert B. Tremaine - Stormville NY, US
Kenneth L. Wright - Austin TX, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 12/00
US Classification:
711154, 711E12001
Abstract:
An embodiment is a method for operating a memory system, the method including storing initial calibration values for each of a first frequency and second frequency for a memory device, performing a periodic calibration to determine a calibration update value for operation of the memory device at the first frequency, combining the calibration update value with the initial calibration value for the first frequency to provide an updated calibration for operation of the memory device at an operating frequency of the first frequency and receiving a frequency change request at a memory controller associated with the memory device. The method further includes blocking traffic to the memory device, adjusting operating frequency to the second frequency while the memory device remains powered, combining the calibration update value with the initial calibration value for the second frequency for operation at the second frequency and enabling traffic to the memory device.

Memory Device Support Of Dynamically Changing Frequency In Memory Systems

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US Patent:
20130262792, Oct 3, 2013
Filed:
Mar 27, 2012
Appl. No.:
13/431108
Inventors:
Joab D. Henderson - Pflugerville TX, US
Ryan J. Pennington - Austin TX, US
Anuwat Saetow - Austin TX, US
Robert B. Tremaine - Stormville NY, US
Kenneth L. Wright - Austin TX, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 12/00
US Classification:
711154, 711E12001
Abstract:
An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.

Processor Noise Mitigation Using Differential Critical Path Monitoring

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US Patent:
20130318364, Nov 28, 2013
Filed:
May 24, 2012
Appl. No.:
13/479797
Inventors:
Michael S. Floyd - Cedar Park TX, US
Jarom Pena - Pflugerville TX, US
Ryan J. Pennington - Austin TX, US
Catherine Sherry - Austin TX, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.

Inference In Memory

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US Patent:
20210373790, Dec 2, 2021
Filed:
May 26, 2020
Appl. No.:
16/883869
Inventors:
- San Diego CA, US
Daniel CAMPBELL - Austin TX, US
Ryan PENNINGTON - Round Rock TX, US
International Classification:
G06F 3/06
G06F 13/16
G06N 20/00
Abstract:
Certain aspects of the present disclosure provide a method for processing data with an enhanced memory module comprising a compute core, including: receiving data at the enhanced memory module from a host processing system; storing the data in host processing system-addressable memory; transferring the data from the host processing system-addressable memory to compute core-addressable memory; processing the data with the compute core on the enhanced memory module to generate processed data; transferring the processed data from the compute core-addressable memory to the host processing system-addressable memory; and providing the processed data to the host processing system via the host processing system-addressable memory.
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Ryan Justin Pennington from Pflugerville, TX, age ~44 Get Report