Search

Ryan W Wuthrich

from Hinesburg, VT
Age ~58
Get Report
Also known as:
Ryan W Wathrich, Ryan H
Phone and address:
838 Buck Hill Rd, Mechanicsburg, VT 05461
(802) 482-7793
Related to:
Maribel Carrion Dejesus, 55
Connected to:
Bryan Wuthrich, 49Kelsey K Wuthrich, 34Martin W Wuthrich, 94Thomas A Wutke, 72Wade W Wutkee, 60Brian C Wuttke, 60Charles H Wuttke, 74Maureen M Wyak, 59Harold E Wyan, 78Randy S Wyand, 68

Ryan Wuthrich Phones & Addresses

  • 838 Buck Hill Rd, Hinesburg, VT 05461 (802) 482-7793
  • 161 Austin Rd, Burlington, VT 05401 (802) 865-0332
  • 25 Laurel Ct, Fishkill, NY 12524
  • Beacon, NY
  • Poughkeepsie, NY

Work

Company: Ibm Mar 2003 Position: Mfg engineering manager

Skills

Manufacturing • Process Engineering • Program Management • Project Management

Industries

Semiconductors

Resumes

Resumes

Ryan Wuthrich Photo 1

Mfg Engineering Manager

View page
Location:
Winooski, VT
Industry:
Semiconductors
Work:
Ibm
Mfg Engineering Manager
Skills:
Manufacturing
Process Engineering
Program Management
Project Management

Publications

Us Patents

Process For Treating A Semiconductor Substrate

View page
US Patent:
6354309, Mar 12, 2002
Filed:
Sep 29, 2000
Appl. No.:
09/671730
Inventors:
Russell H. Arndt - Wappingers Falls NY
Glenn Walton Gale - Austin TX
Karen P. Madden - Poughquag NY
Dario Salgado - Kearny NJ
Ryan Wayne Wuthrich - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21302
US Classification:
134 13, 216 99, 438749, 438753
Abstract:
Semiconductor substrates are contacted with a deionized water solution containing an acidic material.

Incorporation Of Carbon In Silicon/Silicon Germanium Epitaxial Layer To Enhance Yield For Si-Ge Bipolar Technology

View page
US Patent:
6426265, Jul 30, 2002
Filed:
Jan 30, 2001
Appl. No.:
09/774126
Inventors:
Jack Oon Chu - Manhasset Hills NY
Douglas Duane Coolbaugh - Essex Junction VT
James Stuart Dunn - Jericho VT
David R. Greenberg - White Plains NY
David L. Harame - Essex Junction VT
Basanth Jagannathan - Stormville NY
Robb Allen Johnson - South Burlington VT
Louis D. Lanzerotti - Burlington VT
Kathryn Turner Schonenberg - New Fairfield CT
Ryan Wayne Wuthrich - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21331
US Classification:
438312, 438357
Abstract:
A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Optimized Blocking Impurity Placement For Sige Hbts

View page
US Patent:
6744079, Jun 1, 2004
Filed:
Mar 8, 2002
Appl. No.:
09/683983
Inventors:
Basanth Jagannathan - Beacon NY
Alvin J. Joseph - Williston VT
Xuefeng Liu - South Burlington VT
Kathryn T. Schonenberg - Wappingers Falls NY
Ryan W. Wuthrich - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 31072
US Classification:
257197, 257191, 257592
Abstract:
A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Method Of Manufacture Of Mosfet Device With In-Situ Doped, Raised Source And Drain Structures

View page
US Patent:
6774000, Aug 10, 2004
Filed:
Nov 20, 2002
Appl. No.:
10/300239
Inventors:
Wesley C. Natzle - New Paltz NY
Marc W. Cantell - Sheldon VT
Louis D. Lanzerotti - Charlotte VT
Effendi Leobandung - Wappingers Falls NY
Brian L. Tessier - Poughkeepsie NY
Ryan W. Wuthrich - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21336
US Classification:
438300
Abstract:
A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.

Method To Increase Carbon And Boron Doping Concentrations In Si And Sige Films

View page
US Patent:
6780735, Aug 24, 2004
Filed:
Apr 30, 2001
Appl. No.:
09/843783
Inventors:
Basanth Jagannathan - Stormville NY
Jack O. Chu - Manhasset NY
Ryan W. Wuthrich - Burlington VT
Byeongju Park - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2104
US Classification:
438510, 438658
Abstract:
We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Incorporation Of Carbon In Silicon/Silicon Germanium Epitaxial Layer To Enhance Yield For Si-Ge Bipolar Technology

View page
US Patent:
6815802, Nov 9, 2004
Filed:
Apr 15, 2002
Appl. No.:
10/122857
Inventors:
Jack Oon Chu - Manhasset Hills NY
Douglass Duane Coolbaugh - Essex Junction VT
James Stuart Dunn - Jericho VT
David R. Greenberg - White Plains NY
David L. Harame - Essex Junction VT
Basanth Jagannathan - Stormville NY
Robb Allen Johnson - South Burlington VT
Louis D. Lanzerotti - Burlington VT
Kathryn Turner Schonenberg - New Fairfield CT
Ryan Wayne Wuthrich - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27082
US Classification:
257592, 257 12, 257 19, 257 55, 257 63, 257565, 257616
Abstract:
A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Low Defect Pre-Emitter And Pre-Base Oxide Etch For Bipolar Transistors And Related Tooling

View page
US Patent:
6858532, Feb 22, 2005
Filed:
Dec 10, 2002
Appl. No.:
10/316211
Inventors:
Wesley C. Natzle - New Paltz NY, US
David C. Ahlgren - Wappingers Falls NY, US
Steven G. Barbee - Amenia NY, US
Marc W. Cantell - Sheldon VT, US
Basanth Jagannathan - Beacon NY, US
Louis D. Lanzerotti - Burlington VT, US
Seshadri Subbanna - Brewster NY, US
Ryan W. Wuthrich - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/4763
US Classification:
438637, 438639, 438714, 438309
Abstract:
An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Mosfet Device With In-Situ Doped, Raised Source And Drain Structures

View page
US Patent:
6858903, Feb 22, 2005
Filed:
Jun 30, 2004
Appl. No.:
10/881449
Inventors:
Wesley C. Natzle - New Paltz NY, US
Marc W. Cantell - Sheldon VT, US
Louis D. Lanzerotti - Charlotte VT, US
Effendi Leobandung - Wappingers Falls NY, US
Brian L. Tessier - Poughkeepsie NY, US
Ryan W. Wuthrich - Burlington VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L027/76
US Classification:
257368, 257 24, 257 57
Abstract:
A process for manufacturing an FET device. A semiconductor substrate is covered with a gate dielectric layer and with a conductive gate electrode formed over the gate dielectric. Blanket layers of silicon oxide may be added. An optional collar of silicon nitride may be formed over the silicon oxide layer around the gate electrode. Two precleaning steps are performed. Chemical oxide removal gases are then deposited, covering the device with an adsorbed reactant film. The gate dielectric (aside from the gate electrode) is removed, as the adsorbed reactant film reacts with the gate dielectric layer to form a rounded corner of silicon oxide at the base of the gate electrode. One or two in-situ doped silicon layers are deposited over the source/drain regions to form single or laminated epitaxial raised source/drain regions over the substrate protruding beyond the surface of the gate dielectric.
Control profile
Ryan W Wuthrich from Hinesburg, VT, age ~58 Get Report