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Samuel A Steidl

from Palo Alto, CA
Age ~55
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Also known as:
Samuel Aloysius Steidl, Samuel Aloysi Steidl, Samuel Aloysisu Steidl, Samuel Aloysius Steidi
Phone and address:
470 Jacobs Ct, Palo Alto, CA 94306
Related to:
Janel L Nichols, 52Michael L Nichols, 56Jeffrey J Steidl, 51Jonathon F Vangompel, 51Leslie A Haack, 49Gail L Steidl, 51Virginia L Steidl, 82Jill Steidl Nichols, 54
Connected to:
Connie L Steidl, 78Daniel E Steidl, 44Vincent J Steidl, 60Adam L Steidley, 53Jay Steidle, 67Robert Steidley, 70Steven M Steidle, 66Dalia Steier, 51David M Steier, 62Jonathan R Steier, 50

Samuel Steidl Phones & Addresses

  • 470 Jacobs Ct, Palo Alto, CA 94306
  • Hayward, WI
  • 3724 Spencer St, Torrance, CA 90503 (310) 371-0699
  • 20359 Anza Ave, Torrance, CA 90503 (310) 371-0699
  • Redondo Beach, CA
  • Troy, NY
  • Menasha, WI
  • Sayner, WI

Work

Company: Gigoptix inc. May 2015 to Apr 30, 2017 Position: Integrated circuit design engineer

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: Rensselaer Polytechnic Institute 1992 to 2001 Specialities: Electrical Engineering, Philosophy

Skills

Asic • Semiconductors • Analog • Analog Circuit Design • Soc • Mixed Signal • Circuit Design • Electronics • Verilog • Ic • Mixed Signal Ic Design • Debugging

Industries

Semiconductors

Resumes

Resumes

Samuel Steidl Photo 1

Staff Analog Design Engineer

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Location:
130 Baytech Dr, San Jose, CA 95134
Industry:
Semiconductors
Work:
Gigoptix Inc. May 2015 - Apr 30, 2017
Integrated Circuit Design Engineer
Idt - Integrated Device Technology, Inc. May 2015 - Apr 30, 2017
Staff Analog Design Engineer
Semtech Dec 2009 - Dec 2014
Senior Staff Engineer, Analog and Mixed-Signal Design
Sierra Monolithics Jan 2001 - Dec 2009
Senior Staff Engineer, Analog and Mixed-Signal Design
Education:
Rensselaer Polytechnic Institute 1992 - 2001
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering, Philosophy Stanford University 1987 - 1991
Bachelors, Bachelor of Science, Electrical Engineering St. Mary Central High School
Skills:
Asic
Semiconductors
Analog
Analog Circuit Design
Soc
Mixed Signal
Circuit Design
Electronics
Verilog
Ic
Mixed Signal Ic Design
Debugging

Publications

Us Patents

Highly Integrated, High-Speed, Low-Power Serdes And Systems

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US Patent:
7848367, Dec 7, 2010
Filed:
Aug 30, 2007
Appl. No.:
11/896162
Inventors:
Craig A. Hornbuckle - Torrance CA, US
David A. Rowe - Torrance CA, US
Samuel A. Steidl - Torrance CA, US
Inho Kim - Palo Alto CA, US
Assignee:
Sierra Monolithics, Inc. - Redondo Beach CA
International Classification:
H04J 3/02
US Classification:
370537, 370907
Abstract:
High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.

Encoding And Decoding Architecture And Method For Pipelining Encoded Data Or Pipelining With A Look-Ahead Strategy

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US Patent:
7933354, Apr 26, 2011
Filed:
Dec 18, 2006
Appl. No.:
11/641363
Inventors:
Samuel A. Steidl - Torrance CA, US
Peter F. Curran - Torrance CA, US
Assignee:
Semtech Corporation - Camarillo CA
International Classification:
H04L 27/10
US Classification:
375283, 375279, 375244, 375330, 375280, 375281
Abstract:
An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.

Highly Integrated, High-Speed, Low-Power Serdes And Systems

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US Patent:
20040136411, Jul 15, 2004
Filed:
Jan 10, 2003
Appl. No.:
10/338972
Inventors:
Craig Hornbuckle - Torrance CA, US
David Rowe - Torrance CA, US
Thomas Krawczyk - Redondo Beach CA, US
Samuel Steidl - Torrance CA, US
Inho Kim - Palo Alto CA, US
Assignee:
Sierra Monolithics, Inc.
International Classification:
H04J003/02
US Classification:
370/537000, 370/463000, 370/366000
Abstract:
High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher-clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock. A deserializer may include (i) an input receiver circuit for receiving and adjusting an input data signal, (ii) a clock and data recovery circuit (CDR) for recovering clock and data signals, (iii) a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, (iv) a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.
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Samuel A Steidl from Palo Alto, CA, age ~55 Get Report