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Shashi Kiran Chilappagari

from San Jose, CA
Age ~42
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Also known as:
Shashi K Chilappagari, Shashikiran Kiran Chilappagari
Phone and address:
6227 Tillamook Dr, San Jose, CA 95123
(408) 622-8803
Related to:
Pallavi ChilappagariPallavi Chilappagari, 39
Connected to:
Bryan J Chilcher, 55Jennifer E Chilcoat, 59Regina A Chilcoat, 65Chris Chilcott, 63Dawn M Chilcott, 61Malinda R Chilcote, 47Olivia M Chilcote, 34Patricia M Chilcote, 86Shannon Chilcote, 51Steve J Chilcott, 77

Shashi Chilappagari Phones & Addresses

  • 6227 Tillamook Dr, San Jose, CA 95123 (408) 622-8803
  • Tucson, AZ
  • 801 Federal St, Chandler, AZ 85226 (480) 284-8921
  • Los Alamos, NM

Work

Company: University of arizona Jan 2009 Position: Postdoctoral research associate

Education

Degree: Ph.D. School / High School: University of Arizona 2004 to 2008 Specialities: Electrical Engineering

Skills

Ldpc Codes • Nand Flash • Error Correcting Codes • Digital Signal Processing • Channel Coding • Data Path Architecture • Algorithms • System Architecture • Machine Learning • Digital Signal Processors • Hw Development • Fpga Prototyping

Languages

English • Telugu

Industries

Semiconductors

Resumes

Resumes

Shashi Chilappagari Photo 1

Chief Architect

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
University of Arizona since Jan 2009
Postdoctoral Research Associate
University of Arizona Aug 2004 - Dec 2008
Graduate Research Assistant
Los Alamos National Laboratory Jul 2008 - Sep 2008
Graduate Research Associate
IBM May 2006 - Aug 2006
Graduate Student Intern
Moschip Semiconductor May 2002 - Aug 2002
Student Intern
Education:
University of Arizona 2004 - 2008
Ph.D., Electrical Engineering Indian Institute of Technology, Madras 1999 - 2004
B.Tech, Electrical Engineering Indian Institute of Technology, Madras 1999 - 2004
M.Tech, Electrical Engineering
Skills:
Ldpc Codes
Nand Flash
Error Correcting Codes
Digital Signal Processing
Channel Coding
Data Path Architecture
Algorithms
System Architecture
Machine Learning
Digital Signal Processors
Hw Development
Fpga Prototyping
Languages:
English
Telugu

Publications

Us Patents

Determining Optimal Reference Voltages For Progressive Reads In Flash Memory Systems

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US Patent:
8531888, Sep 10, 2013
Filed:
Jun 24, 2011
Appl. No.:
13/167896
Inventors:
Shashi Kiran Chilappagari - San Jose CA, US
Xueshi Yang - Cupertino CA, US
Assignee:
Marvell World Trade Ltd. - St. Michael
International Classification:
G11C 11/34
US Classification:
3651852, 36518503, 36518505, 36518518, 36518519, 36518521, 36518524, 365189011, 36518915
Abstract:
A system including a reference voltage module to select a first reference voltage between a first threshold voltage corresponding to a first state of a memory cell and a second threshold voltage corresponding to a second state of the memory cell, a second reference voltage less than the first reference voltage, and a third reference voltage greater than the first reference voltage. The system includes a read module to perform a first read operation to determine a state of the memory cell based on the first reference voltage, and in response to a first failure to decode data read from the memory cell in the first read operation, perform a second read operation to determine the state based on the second reference voltage and a third read operation to determine the state based on the third reference voltage.

Decoder Parameter Estimation Using Multiple Memory Reads

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US Patent:
8576625, Nov 5, 2013
Filed:
Apr 18, 2011
Appl. No.:
13/089135
Inventors:
Xueshi Yang - Cupertino CA, US
Shashi Kiran Chilappagari - San Jose CA, US
Assignee:
Marvell International Ltd. - Hamilton
International Classification:
G11C 16/06
US Classification:
36518509, 36518518, 3651852
Abstract:
An apparatus including a memory array and control circuitry. The control circuitry is configured to, based at least on a plurality of read comparison results, determine a number of memory cells of the memory array that have threshold voltages that fall into each of a plurality of voltage ranges. The control circuitry is further configured to, based at least on the number of memory cells that have threshold voltages in each of the plurality of voltage ranges, estimate an offset amount that a center voltage between two threshold voltage distributions differs from a center reference voltage. The control circuitry is further configured to read one or more of the plurality of memory cells based at least in part on the estimated offset amount.

Low Complexity Finite Precision Decoders And Apparatus For Ldpc Codes

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US Patent:
20110087946, Apr 14, 2011
Filed:
Oct 8, 2010
Appl. No.:
12/900584
Inventors:
Shiva K. PLANJERY - Tucson AZ, US
Shashi Kiran CHILAPPAGARI - San Jose CA, US
Bane VASIC - Tucson AZ, US
David DECLERCQ - Ableiges, FR
Assignee:
University of Cergy-Pontoise - Cergy-Pontoise cedex
University of Arizona - Tucson AZ
International Classification:
H03M 13/05
G06F 11/10
US Classification:
714752, 714E11032
Abstract:
In this invention, a new class of finite precision multilevel decoders for low-density parity-check (LDPC) codes is presented. These decoders are much lower in complexity compared to the standard belief propagation (BP) decoder. Messages utilized by these decoders are quantized to certain levels based on the number of bits allowed for representation in hardware. A message update function specifically defined as part of the invention, is used to determine the outgoing message at the variable node, and the simple min operation along with modulo 2 sum of signs is used at the check node. A general methodology is provided to obtain the multilevel decoders, which is based on reducing failures due to trapping sets and improving the guaranteed error-correction capability of a code. Hence these decoders improve the iterative decoding process on finite length graphs and have the potential to outperform the standard floating-point BP decoder in the error floor region. The description and apparatus of 3-bit decoders for column-weight three LDPC codes is also presented.

Methods And Systems For Encoding And Decoding In Trellis Coded Modulation Systems

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US Patent:
20120110410, May 3, 2012
Filed:
Oct 31, 2011
Appl. No.:
13/285327
Inventors:
Shashi Kiran Chilappagari - San Jose CA, US
Xueshi Yang - Cupertino CA, US
International Classification:
H03M 13/07
H03M 13/29
G06F 11/10
H03M 13/27
H03M 13/23
US Classification:
714756, 714755, 714E11032
Abstract:
Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data.

Mapping Data To Non-Volatile Memory

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US Patent:
20120198135, Aug 2, 2012
Filed:
Jan 27, 2012
Appl. No.:
13/360626
Inventors:
Shashi Kiran Chilappagari - San Jose CA, US
Xueshi Yang - Cupertino CA, US
Gregory Burd - San Jose CA, US
International Classification:
G06F 12/02
G06F 12/06
G06F 12/00
US Classification:
711103, 711101, 711206, 711E12078, 711E12008, 711E12001
Abstract:
The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Systems And Methods For Generating Soft Information In Nand Flash

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US Patent:
20120300545, Nov 29, 2012
Filed:
May 22, 2012
Appl. No.:
13/477678
Inventors:
Zhengang Chen - San Jose CA, US
Gregory Burd - San Jose CA, US
Shashi Kiran Chilappagari - San Jose CA, US
Xueshi Yang - Cupertino CA, US
Assignee:
E I DU PONT DE NEMOURS AND COMPANY - Wilmington DE
International Classification:
G11C 16/06
US Classification:
3651852
Abstract:
Systems and methods are provided to generate soft information related to the threshold voltage of a memory cell. A range of threshold voltages for the memory cell is divided into subregions of threshold voltage values herein referred to as bins. An output of the memory cell in response to an applied reference signal is measured. The applied reference signal includes a voltage value and position information. A single bin is identified based on the position information of the reference signal. The identified bin is split into more than one bin based on the output of the memory cell and the voltage value of the reference signal. The newly split bins and all the other bins that were not split are assigned new bin indices.

Identification And Mitigation Of Hard Errors In Memory Systems

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US Patent:
20120317460, Dec 13, 2012
Filed:
May 25, 2012
Appl. No.:
13/481376
Inventors:
Shashi Kiran Chilappagari - San Jose CA, US
Gregory Burd - San Jose CA, US
Zhengang Chen - San Jose CA, US
International Classification:
H03M 13/05
G06F 11/10
G11C 16/04
US Classification:
714773, 36518505, 714E11035
Abstract:
Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation.

Symbol Flipping Decoders Of Non-Binary Low-Density Parity Check (Ldpc) Codes

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US Patent:
20140068393, Mar 6, 2014
Filed:
Aug 23, 2013
Appl. No.:
13/974901
Inventors:
- St. Michael, BB
Shashi Kiran Chilappagari - San Jose CA, US
Assignee:
MARVELL WORLD TRADE LTD. - St. Michael
International Classification:
H03M 13/25
US Classification:
714786
Abstract:
Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances.
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Shashi Kiran Chilappagari from San Jose, CA, age ~42 Get Report