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Shengquan Ou Phones & Addresses

  • 1825 Ray Rd, Chandler, AZ 85224 (480) 726-1526
  • 3120 Sawtelle Blvd, Los Angeles, CA 90066 (310) 390-5690
  • 3140 Sawtelle Blvd, Los Angeles, CA 90066 (310) 390-5690
  • Maricopa, AZ

Publications

Us Patents

Interconnect Joint

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US Patent:
20090020869, Jan 22, 2009
Filed:
Jul 17, 2007
Appl. No.:
11/779110
Inventors:
Qing Xue - Tempe AZ, US
Shengquan E. Ou - Chandler AZ, US
Sairam Agraharam - Phoenix AZ, US
International Classification:
H01L 23/48
US Classification:
257737, 257E23021
Abstract:
An interconnect joint comprises a substrate (), a solder resist layer () over the substrate, a solder resist opening () (having a top surface ()) in the solder resist layer, a solder material () in the solder resist opening, and an electrically conducting structure () having a portion that extends into the solder material below the top of the solder resist opening.

Multi-Chip Packaging

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US Patent:
20220231007, Jul 21, 2022
Filed:
Apr 8, 2022
Appl. No.:
17/716934
Inventors:
- Santa Clara CA, US
Sairam AGRAHARAM - Chandler AZ, US
Shengquan OU - Chandler AZ, US
Thomas J. DE BONIS - Tempe AZ, US
Todd SPENCER - Chandler AZ, US
Yang SUN - Chandler AZ, US
Guotao WANG - Chandler AZ, US
International Classification:
H01L 25/00
H01L 23/00
H01L 23/538
H01L 25/18
H01L 21/56
Abstract:
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Multi-Chip Packaging

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US Patent:
20200395352, Dec 17, 2020
Filed:
Jun 4, 2020
Appl. No.:
16/892698
Inventors:
- Santa Clara CA, US
Sairam Agraharam - Chandler AZ, US
Shengquan Ou - Chandler AZ, US
Thomas J. De Bonis - Tempe AZ, US
Todd Spencer - Chandler AZ, US
Yang Sun - Chandler AZ, US
Guotao Wang - Chandler AZ, US
International Classification:
H01L 25/00
H01L 23/538
H01L 25/18
H01L 23/00
H01L 21/56
Abstract:
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Multi-Chip Packaging

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US Patent:
20190371778, Dec 5, 2019
Filed:
Jun 4, 2018
Appl. No.:
15/996870
Inventors:
- Santa Clara CA, US
Sairam Agraharam - Chandler AZ, US
Shengquan Ou - Chandler AZ, US
Thomas J. De Bonis - Tempe AZ, US
Todd Spencer - Santa Clara CA, US
Yang Sun - Chandler AZ, US
Guotao Wang - Chandler AZ, US
International Classification:
H01L 25/00
H01L 21/56
H01L 23/538
H01L 25/18
H01L 23/00
Abstract:
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

Structures To Mitigate Contamination On A Back Side Of A Semiconductor Substrate

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US Patent:
20170186707, Jun 29, 2017
Filed:
Dec 23, 2015
Appl. No.:
14/998096
Inventors:
- Santa Clara CA, US
Shweta AGRAWAL - Gilbert AZ, US
Hao WU - Chandler AZ, US
Mohit MAMODIA - Chandler AZ, US
Shengquan E. OU - Chandler AZ, US
Hualiang SHI - Chandler AZ, US
International Classification:
H01L 23/58
H01L 21/78
H01L 21/768
H01L 23/48
H01L 23/528
Abstract:
Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Die Connections Using Different Underfill Types For Different Regions

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US Patent:
20150001736, Jan 1, 2015
Filed:
Jun 29, 2013
Appl. No.:
13/931909
Inventors:
Hualiang Shi - Chandler AZ, US
Shengquan Ou - Chandler AZ, US
Sairam Agraharam - Chandler AZ, US
Shan Zhong - Chandler AZ, US
Sivakumar Nagarajan - Chandler AZ, US
Weihua Tang - Chandler AZ, US
International Classification:
H01L 21/762
H01L 25/065
US Classification:
257777, 438455
Abstract:
Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

Solution To Deal With Die Warpage During 3D Die-To-Die Stacking

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US Patent:
20150001740, Jan 1, 2015
Filed:
Jun 28, 2013
Appl. No.:
13/930889
Inventors:
Hualiang SHI - Chandler AZ, US
Shengquan E. OU - Chandler AZ, US
Sairam AGRAHARAM - Chandler AZ, US
Tyler N. OSBORN - Gilber AZ, US
International Classification:
H01L 21/768
H01L 23/498
US Classification:
257784, 438612
Abstract:
A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.
Shengquan Ou from Chandler, AZ, age ~49 Get Report