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Sovandy N Prak

from Meridian, ID
Age ~62
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Also known as:
Sovandy Nicolas Prak, Sovandy P Prak, Savandy N Prak, Y Prak
Phone and address:
4230 Venture St, Meridian, ID 83642
(208) 323-2153
Related to:
Kris PrakViseth S Kheang, 51Isaac L Kheang, 56Yukheng K Kheang, 71Kristopher S Prak, 28Yukheng Kheang, 85Seila Kheang, 44Helena K Prak, 57Nicolas Prak, 29Madeleine M Prak, 26
Connected to:
Channary M Prak, 55Vanna Prak, 68Ruth M Prakasam, 52Ajay Prakash, 63Anaka K Prakash, 77Chakrapani T Prakash, 70Gaurav A Prakash, 36Hari Prakash, 55Heather K Prakash, 51Paranji R Prakash, 87

Sovandy Prak Phones & Addresses

  • 4230 Venture St, Meridian, ID 83642 (208) 323-2153
  • 4230 Venture Pl, Meridian, ID 83642 (208) 323-2153
  • Lynnwood, WA
  • 6730 154Th St, Snohomish, WA 98296 (425) 379-7056
  • Boise, ID
  • Chippewa Falls, WI
  • Chippewa Falls, WI

Resumes

Resumes

Sovandy Prak Photo 1

Test Engineer, Ssd

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Location:
4230 east Venture Pl, Meridian, ID 83646
Industry:
Semiconductors
Work:
Micron Technology Sep 2001 - Nov 2013
Test Engineer, Dram
Micron Technology Sep 2001 - Nov 2013
Test Engineer, Ssd
Micron Electronic Oct 1997 - Feb 2000
Test Program Designer and Developer
Micron Electronic Aug 1993 - Oct 1997
Test Engineering Manager, Spectek Division
Micron Technology Sep 1990 - Aug 1993
Test Engineer
Interests:
Kids
Exercise
Electronics
Traveling
Gardening
Home Improvement
Reading
Automobiles
Travel
Collecting
Languages:
English
Sovandy Prak Photo 2

Test Engineer

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Location:
Meridian, ID
Industry:
Semiconductors
Work:
Micron Technology
Test Engineer

Publications

Us Patents

Processing Semiconductor Devices Having Some Defective Input-Output Pins

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US Patent:
6778933, Aug 17, 2004
Filed:
Dec 10, 2002
Appl. No.:
10/315594
Inventors:
David Charlton - Star ID
Sovandy Prak - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 2900
US Classification:
702118, 702117
Abstract:
Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.

Method And Apparatus For Storing Failing Part Locations In A Module

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US Patent:
7890819, Feb 15, 2011
Filed:
Mar 19, 2007
Appl. No.:
11/725292
Inventors:
David E. Charlton - Star ID, US
Sovandy N. Prak - Meridian ID, US
Keith E. Robinson - Caldwell ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 29/00
G11C 7/00
G06F 11/00
US Classification:
714710, 714 42, 365201
Abstract:
A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module, such as data query (“DQ”) terminals, identified during a testing procedure. After testing, the non-volatile storage device, such as an electrically erasable programmable read only memory (“EEPROM”), may be accessed to determine specific memory devices such as dynamic random access memory (“DRAM”) which need to be repaired or replaced rather than re-testing the specific memory module.

Method And Apparatus For Storing Failing Part Locations In A Module

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US Patent:
7269765, Sep 11, 2007
Filed:
Apr 13, 2000
Appl. No.:
09/548826
Inventors:
David E. Charlton - Star ID, US
Sovandy N. Prak - Meridian ID, US
Keith E. Robinson - Caldwell ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 29/00
G11C 7/00
G06F 11/00
US Classification:
714710, 714 42, 365201
Abstract:
A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module, such as data query (“DQ”) terminals, identified during a testing procedure. After testing, the non-volatile storage device, such as an electrically erasable programmable read only memory (“EEPROM”), may be accessed to determine specific memory devices such as dynamic random access memory (“DRAM”) which need to be repaired or replaced rather than re-testing the specific memory module.

Processing Semiconductor Devices Having Some Defective Input-Output Pins

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US Patent:
6510443, Jan 21, 2003
Filed:
Dec 7, 1998
Appl. No.:
09/207090
Inventors:
David Charlton - Star ID
Sovandy Prak - Meridian ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 2900
US Classification:
708118, 702117, 365201
Abstract:
Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.
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Sovandy N Prak from Meridian, ID, age ~62 Get Report