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Sreeker Reddy Dundigal

from San Diego, CA
Age ~41
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Also known as:
Sreeker R Dundigal, Sreeker L
Phone and address:
12360 Creekview Dr, San Diego, CA 92128
Connected to:
Jason M Dundis, 43Eric J Dundon, 45Julie Dundon, 63Kelly M Dundon, 37Lori M Dundon, 54Sandra J Dundon, 77Anil DundooDavid L Dundore, 63Jonathan A Dundore, 46Miles A Dundore, 75

Sreeker Dundigal Phones & Addresses

  • 12360 Creekview Dr, San Diego, CA 92128
  • Atlanta, GA
  • Peoria, IL
  • Las Cruces, NM

Work

Company: Qualcomm Apr 2016 Position: Principal engineer and manager

Education

Degree: Master of Science, Masters School / High School: New Mexico State University 2003 to 2005

Skills

Asic • Vlsi • Cmos • Mixed Signal • Soc • Circuit Design • Cadence Virtuoso • Phy • Eda • Lvs • Esd • Tlp • Static Timing Analysis • Esd Control • Simulations

Industries

Semiconductors

Resumes

Resumes

Sreeker Dundigal Photo 1

Principal Engineer And Manager

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Location:
San Diego, CA
Industry:
Semiconductors
Work:
Qualcomm
Principal Engineer and Manager
Qualcomm Oct 2012 - Apr 2016
Staff Engineer, Esd Design Lead
Qualcomm Oct 2008 - Oct 2012
Senior Engineer, Esd Design Lead
Qualcomm May 2006 - Oct 2008
Engineer, Esd and Io Design
Education:
New Mexico State University 2003 - 2005
Master of Science, Masters Jawaharlal Nehru Technological University 1999 - 2003
Bachelors, Bachelor of Technology
Skills:
Asic
Vlsi
Cmos
Mixed Signal
Soc
Circuit Design
Cadence Virtuoso
Phy
Eda
Lvs
Esd
Tlp
Static Timing Analysis
Esd Control
Simulations

Publications

Us Patents

Method And Apparatus For Forming I/O Clusters In Integrated Circuits

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US Patent:
8184414, May 22, 2012
Filed:
Jul 30, 2008
Appl. No.:
12/182454
Inventors:
Reza Jalilizeinali - Oceanside CA, US
Sreeker Dundigal - San Diego CA, US
Vivek Mohan - San Diego CA, US
Thomas R. Toms - Dripping Springs TX, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.

Distributed Building Blocks Of R-C Clamping Circuitry In Semiconductor Die Core Area

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US Patent:
8531806, Sep 10, 2013
Filed:
Jun 30, 2011
Appl. No.:
13/173977
Inventors:
Reza Jalilizeinali - San Diego CA, US
Sreeker R. Dundigal - San Diego CA, US
Eugene R. Worley - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H02H 3/22
US Classification:
361 56, 361111
Abstract:
A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.

System And Method For Excess Voltage Protection In A Multi-Die Package

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US Patent:
20100039740, Feb 18, 2010
Filed:
Aug 12, 2008
Appl. No.:
12/190158
Inventors:
Reza Jalilizeinali - Oceanside CA, US
Sreeker Dundigal - San Diego CA, US
Vivek Mohan - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H02H 9/00
H01L 21/66
US Classification:
361 56, 438 13, 257E21531
Abstract:
A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.

Active Diode Having No Gate And No Shallow Trench Isolation

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US Patent:
20110084362, Apr 14, 2011
Filed:
Mar 31, 2010
Appl. No.:
12/751903
Inventors:
Reza Jalilizeinali - Oceanside CA, US
Eugene R. Worley - Irvine CA, US
Sreeker R. Dundigal - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H01L 29/861
H01L 21/762
US Classification:
257546, 438433, 257E29327, 257E21546
Abstract:
An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed.

Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same

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US Patent:
20120074496, Mar 29, 2012
Filed:
Mar 30, 2011
Appl. No.:
13/075701
Inventors:
Reza Jalilizeinali - San Diego CA, US
Eugene R. Worley - San Diego CA, US
Sreeker Dundigal - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H01L 23/62
B05C 11/00
H01L 21/762
H01L 29/78
H01L 29/861
US Classification:
257355, 257288, 257510, 438400, 118504
Abstract:
Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.

Interface Circuit With Robust Electrostatic Discharge

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US Patent:
20230008489, Jan 12, 2023
Filed:
Jul 8, 2021
Appl. No.:
17/370894
Inventors:
- San Diego CA, US
Reza JALILIZEINALI - San Marcos CA, US
Sreeker DUNDIGAL - San Diego CA, US
Krishna Chaitanya CHILLARA - Del Mar CA, US
Gregory LYNCH - San Diego CA, US
International Classification:
H02H 9/04
H01L 27/02
Abstract:
An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad. The gate pull transistor may be configured to provide a low impedance path between the gate of the driver transistor and the I/O pad or the first rail when an overvoltage signal applied to the I/O pad has a magnitude that exceeds the nominal operating range of voltage levels defined for the I/O pad.

Die-To-Die Interface Configuration And Methods Of Use Thereof

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US Patent:
20180233907, Aug 16, 2018
Filed:
Feb 16, 2017
Appl. No.:
15/434285
Inventors:
- San Diego CA, US
Luverne Ray Peterson - San Diego CA, US
Thomas Bryan - Carlsbad CA, US
Stephen Knol - San Diego CA, US
Sreeker Dundigal - San Diego CA, US
Alvin Loke - San Diego CA, US
International Classification:
H02H 9/04
H01L 23/00
H01L 27/02
H01L 23/485
H01L 23/50
H01L 25/065
Abstract:
A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.

Bulk Cross-Coupled High Density Power Supply Decoupling Capacitor

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US Patent:
20170352651, Dec 7, 2017
Filed:
Jun 2, 2016
Appl. No.:
15/171987
Inventors:
- San Diego CA, US
Hai DANG - San Diego CA, US
Sreeker DUNDIGAL - San Diego CA, US
Vasisht VADI - San Diego CA, US
International Classification:
H01L 27/02
H01L 29/786
H01L 29/10
H01L 29/94
H01L 27/06
Abstract:
In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.
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Sreeker Reddy Dundigal from San Diego, CA, age ~41 Get Report