Stephen Paul Sample

6353552, Mar 5, 2002

Mar 26, 2001

09/817951

Stephen P. Sample - Saratoga CA
Michael R. Butts - Portland OR
Kevin A. Norman - Belmont CA
Rakesh H. Patel - Cupertino CA
Chao Chiang Chen - Cupertino CA

Altera Corporation - San Jose CA
Quickturn Design Systems, Inc. - Mountain View CA

G11C 700

365154, 36518908

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

6377911, Apr 23, 2002

Jul 12, 1999

09/351997

Stephen P. Sample - Mountain View CA
Michael R. DAmour - Los Altos Hills CA
Thomas S. Payne - Union City CA

Quickturn Design Systems, Inc. - San Jose CA

G06G 778

703 24, 702118, 714725, 716 6

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a users circuit or system. A network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

6377912, Apr 23, 2002

Aug 13, 1999

09/374444

Stephen P. Sample - Saratoga CA
Mikhail Bershteyn - Campbell CA
Michael R. Butts - Portland CA
Jerry R. Bauer - Cupertino CA

Quickturn Design Systems, Inc. - San Jose CA

G06F 9455

703 28, 716 1

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

6567967, May 20, 2003

Jun 4, 2001

09/874942

Yaacov I. Greidinger - Herzia, IL
David S. Reed - Los ALtos CA
Ara Markosian - Cupertino CA
Stephen P. Sample - Saratoga CA
Jonathan A. Frankle - Los Gatos CA
Hasmik Lazaryan - Yerevan, AM

Monterey Design Systems, Inc. - Sunnyvale CA

G06F 945

716 10, 716 7, 716 12

An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.

6570404, May 27, 2003

Mar 26, 1997

08/824535

Kevin A. Norman - Belmont CA
Rakesh H. Patel - Cupertino CA
Stephen P. Sample - Saratoga CA
Michael R. Butts - Portland OR

Altera Corporation - San Jose CA

H03K 19177

326 39, 326 40, 326 41, 326 38

A programmable logic device architecture. This programmable logic architecture includes a first logic block ( ) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface ( ), which interfaces with the first logic block ( ), for performing JTAG functions, configuring the first logic block ( ), initializing the first logic block ( ), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block ( ) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network ( ). The first logic block ( ) includes a plurality of second logic blocks ( ) which may be programmably coupled using a second programmable interconnect network ( ). The second programmable interconnect network ( ) may be programmably coupled to the first programmable interconnect network ( ). Furthermore, the plurality of second logic blocks ( ) include a plurality of third logic blocks ( ) which may be programmably coupled using a third programmable interconnect network ( ).

6625793, Sep 23, 2003

Sep 6, 2001

09/949006

Stephen P. Sample - Saratoga CA
Michael R. Butts - Portland OR

Quickturn Design Systems, Inc. - San Jose CA

G06F 1750

716 12, 326 39

A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic.

6694464, Feb 17, 2004

Oct 23, 2000

09/695103

Barton L. Quayle - San Jose CA
Stephen P. Sample - Saratoga CA

Quickturn Design Systems, Inc. - San Jose CA

G01R 3128

714725, 714735, 714736

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.

6732068, May 4, 2004

Aug 2, 2001

09/922113

Stephen P. Sample - Saratoga CA
Mikhail Bershteyn - Campbell CA
Michael R. Butts - Portland OR
Jerry R. Bauer - Cupertino CA

Quickturn Design Systems Inc. - San Jose CA

G06F 9455

703 24, 703 23, 703 25, 703 27, 703 28, 326 40, 712 14, 712 15

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.