Sunil J Parthasarathy

7345897, Mar 18, 2008

Jun 1, 2006

11/444730

Sriram Chitoor Krishnan - San Jose CA, US
Rina Panigrahy - Sunnyvale CA, US
Sunil Parthasarathy - San Jose CA, US

Cisco Technology, Inc. - San Jose CA

G11C 15/00

365 49, 365205, 711108, 711158

Ternary content-addressable memory (TCAM) entries are disclosed for use in performing error-protected lookup operations by allowing an error budget of u deviations in values stored in each entry. Each TCAM entry is configured to identify a hit condition (else a miss condition) with an input lookup word if its stored value matches each bit of the lookup word with the exception of zero to u of its cells not matching. This determination may be made, for example, using discrete logic or based a voltage level of one or more match lines. Furthermore, it is possible to store at least 2u+1 copies of a data value desired to be protected in a such a TCAM entry among its said t TCAM cells.

7349230, Mar 25, 2008

Aug 2, 2006

11/498609

Sunil Parthasarathy - San Jose CA, US
Sriram Chitoor Krishnan - San Jose CA, US

Cisco Technology, Inc. - San Jose CA

G11C 15/00

365 49, 36518907, 365168, 711108

Associative memory bit cells are disclosed for selectively producing binary or ternary content-addressable memory lookup results. Associative memory bit cells are grouped together to act as n binary content-addressable memory cells (CAM) bits or m ternary content-addressable memory (TCAM) bits, with n>m>0. Based on the programming of the associative memory bit cells and the selective application of search values (based on whether they are acting as CAM or TCAM bit cells), the appropriate determination is made as to whether or not to signal a hit or a miss based on the current input search values. These associative memory bit cells can also be combined to provide error protection for either of their operating modes. Error protection can be used to enable a correct result when e bit errors occur in the stored values in the associative memory bit cells.

20070088909, Apr 19, 2007

Oct 18, 2005

11/252960

Sriram Chitoor Krishnan - San Jose CA, US
Sunil Parthasarathy - San Jose CA, US

CISCO TECHNOLOGY, INC., A CALIFORNIA CORPORATION - SAN JOSE CA

G06F 12/00

711108000

A content-addressable memory entry is identified as being matched if it matches all bit positions of a lookup word or does not match for less than a predetermined number of bit positions. A match line of the content-addressable memory entry is precharged. During a subsequent matching phase, each of the bit positions of the content-addressable memory entry provides a discharge path for the precharged match line. Whether or not the content-addressable memory should be identified as being matched is then determined typically by comparing the match reference voltage of the match line to a predetermined voltage level at a predetermined time, with the predetermined voltage level and predetermined time selected for the allowed number of bit positions that do not have to be matched while still considering the content-addressable memory entry to have been matched, and the implementation technology of the embodiment.