Tatyana N Andryushchenko

7223685, May 29, 2007

Jun 23, 2003

10/602488

Tatyana N. Andryushchenko - Portland OR, US
Anne E. Miller - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 21/4763
H01L 21/44
H01L 21/461
H01L 21/302

438622, 438625, 438626, 438627, 438628, 438629, 438631, 438633, 438634, 438637, 438638, 438643, 438644, 438645, 438648, 438652, 438653, 438654, 438656, 438669, 438672, 438685, 438687, 438691, 438692, 257E2101, 257E21011

The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer. Also disclosed is an apparatus comprising a vessel having an electrolyte therein, a first electrode at least partially immersed in the electrolyte, the first electrode comprising a wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD layer, a barrier layer deposited on the under-layer and a conductive layer deposited in the feature, a second electrode at least partially immersed in the electrolyte, and a potential source for applying a potential difference between the first and second electrodes. Other embodiments are also disclosed and claimed.

7560380, Jul 14, 2009

Oct 27, 2006

11/588982

Tatyana N. Andryushchenko - Portland OR, US
Anne E. Miller - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 21/20

438637, 438628, 438653, 438656, 438687, 257E21017, 257E21303, 257E21309, 257E21583, 257E21588

A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

7585760, Sep 8, 2009

Jun 23, 2006

11/473738

Tatyana N. Andryushchenko - Portland OR, US
Anne E. Miller - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 21/4763

438626, 257752, 257E23145

Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e. g. , aluminum) over first conductive film (e. g. , copper) deposited in an opening formed in a dielectric layer (e. g. , low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.

8637778, Jan 28, 2014

Apr 8, 2010

12/756748

Qing Ma - Saratoga CA, US
Jun He - Portland OR, US
Patrick Morrow - Portland OR, US
Paul B. Fischer - Portland OR, US
Sridhar Balakrishnan - Portland OR, US
Satish Radhakrishnan - Hillsboro OR, US
Tatyana Tanya Andryushchenko - Portland OR, US
Guanghai Xu - Portland OR, US

Intel Corporation - Santa Clara CA

H05K 1/03
H05K 7/02

174260, 174255, 174263, 361792, 361807, 361809

The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

20030234182, Dec 25, 2003

Jun 19, 2002

10/175671

Tatyana Andryushchenko - Portland OR, US

C25D007/12

205/157000

A copper damascene process for a mechanically weak low k dielectric layer is described. Electropolishing is used to etch back the copper. A sacrificial conductive layer beneath the barrier layer assures complete planarization of the copper.

20040256224, Dec 23, 2004

Oct 3, 2003

10/679141

Tatyana Andryushchenko - Portland OR, US
Anne Miller - Portland OR, US

C25D017/10

204/290030

The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer. Also disclosed is an apparatus comprising a vessel having an electrolyte therein, a first electrode at least partially immersed in the electrolyte, the first electrode comprising a wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD layer, a barrier layer deposited on the under-layer and a conductive layer deposited in the feature, a second electrode at least partially immersed in the electrolyte, and a potential source for applying a potential difference between the first and second electrodes. Other embodiments are also disclosed and claimed.

20070152252, Jul 5, 2007

Dec 30, 2005

11/322885

Mark Buehler - Portland OR, US
Anne Miller - Portland OR, US
Tatyana Andryushchenko - Portland OR, US

H01L 21/8242
H01L 21/461

257295000, 438585000, 438633000, 438692000, 438240000, 438591000, 438785000, 257382000

A method for reducing the dissolution of aluminum gate electrodes in a high pH clean chemistry comprises modifying the high pH clean chemistry to include a silanol-based chemical. The silanol-based chemical causes a protective layer to form on a top surface of the aluminum gate electrode. The protective layer substantially reduces or prevents corrosion that occurs due to the high pH level of the clean chemistry. The protective layer is formed by the silanol-based chemical bonding to the aluminum gate electrode through a hydrolysis reaction, thereby forming a silanol-based protective layer.

20070228011, Oct 4, 2007

Mar 31, 2006

11/396012

Mark Buehler - Portland OR, US
Mandyam Sriram - Beaverton OR, US
Danilo Castillo-Mejia - Hillsboro OR, US
Tatyana Andryushchenko - Portland OR, US

B44C 1/22
C09K 13/00
C03C 15/00

216083000, 216088000, 216089000, 216100000, 252079100

A chemical composition and methods to remove defects while maintaining corrosion protection of conductors on a substrate are described. The composition includes a conductive solution, a corrosion inhibitor; and a surfactant. A surfactant-to-inhibitor ratio in the composition is a function of a metal. The surfactant is an anionic surfactant, a non-ionic surfactant, or any combination thereof. The concentration of the corrosion inhibitor in the chemical composition can be low. The corrosion inhibitor can form soft bonds with a conductor material. The conductive solution can be a high ionic strength solution. The composition is applied to a wafer having conductors on a substrate. At least two conductors on the substrate have different potentials. The composition can be used to clean the wafer after forming the conductors on the substrate. The composition can be used for chemical mechanical polishing of the wafer.