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Tim P Lao

from Sacramento, CA
Age ~56
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Also known as:
Tim Phuoc Lao, Timothy Lao
Phone and address:
2968 N Platte Way, Sacramento, CA 95835
Related to:
Ann LaoKim Lao, 54Michael J Irwin, 55Robert L Goodman, 59Tony T Troung, 85Duke P Lao, 52Woon C Kim, 39
Connected to:
Agnes C Lao, 56Anne W Lao, 68Carol F Lao, 77Chai N Lao, 42Cong O LaoDonna Lao, 32George S Lao, 62Luis E Lao, 35Mona L Lao, 55Neal J Lao, 50

Tim Lao Phones & Addresses

  • 2968 N Platte Way, Sacramento, CA 95835
  • 5713 Tres Piezas Dr, Sacramento, CA 95835
  • 2025 Pyxie Way, Woodbridge, VA 22192
  • 247 Capitol Ave, San Jose, CA 95127
  • 259 Capitol Ave, San Jose, CA 95127
  • 87 Jacklin Rd, Milpitas, CA 95035 (408) 263-0867
  • Chesterfield, VA

Work

Company: Synopsys Apr 2011 to May 2014 Position: Senior r and d engineer

Education

Degree: Masters School / High School: Georgia Institute of Technology 1987 to 1993 Specialities: Electronics Engineering, Electronics

Skills

Simulations • Microprocessors • Testing • Pll • Sram • R&D • Dram • Patents

Industries

Semiconductors

Resumes

Resumes

Tim Lao Photo 1

Tim Lao

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Location:
Sacramento, CA
Industry:
Semiconductors
Work:
Synopsys Apr 2011 - May 2014
Senior R and D Engineer
Emls America Nov 2006 - Oct 2008
Senior Design Engineer
Idt - Integrated Device Technology, Inc. Oct 2005 - Nov 2006
Senior Design Engineer
Bae Systems Sep 2004 - Jun 2005
Electrical Engineer
Uspto Sep 2003 - Aug 2004
Patent Examiner
Education:
Georgia Institute of Technology 1987 - 1993
Masters, Electronics Engineering, Electronics
Skills:
Simulations
Microprocessors
Testing
Pll
Sram
R&D
Dram
Patents

Publications

Us Patents

Driving Memory Bitlines Using Boosted Voltage

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US Patent:
59333863, Aug 3, 1999
Filed:
Dec 23, 1997
Appl. No.:
8/997509
Inventors:
Robert Walker - Rougemont NC
Stephen Camacho - Durham NC
Tim Lao - San Jose CA
Assignee:
Mitsubishi Semiconductor America, Inc. - Durham NC
International Classification:
G11C 800
US Classification:
36523001
Abstract:
An apparatus for driving a bitline driver of a memory array is disclosed. The memory array has row lines, complementary pairs of bitlines driven by bitline drivers, and memory cells at the intersections of the bitlines and the row lines. First and second complementary write data lines provide a bit to be written to the driver and a complement of the bit. A source of a boosted voltage is coupled to a level shifter that conducts the boosted voltage to the bitline driver when the write enable line and the first write data line are asserted. The data bit is latched through a bistable latch to the bitline driver when the write enable line is asserted. A method of driving a bitline of a memory array involves receiving a data bit to be written to the bitline and a complement of the data bit; boosting one of the data bits to a voltage of a magnitude greater than a supply voltage of the memory array; and driving the data bit to a bitline driver.

System And Method For Column Access In Random Access Memories

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US Patent:
62790714, Aug 21, 2001
Filed:
Jul 7, 1998
Appl. No.:
9/111277
Inventors:
Robert M. Walker - Rougemont NC
Tim Lao - San Jose CA
Stephen Camacho - Durham NC
Assignee:
Mitsubishi Electric and Electronics USA, Inc. - Durham NC
International Classification:
G06F 1200
G11C 710
G11C 806
US Classification:
711104
Abstract:
A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.

Dual Clocking Scheme In A Multi-Port Ram

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US Patent:
59599375, Sep 28, 1999
Filed:
Feb 17, 1998
Appl. No.:
9/024559
Inventors:
William L. Randolph - Durham NC
Rhonda Cassada - Hillsborough NC
Tim Lao - San Jose CA
Assignee:
Mitsubishi Semiconductor America, Inc. - Durham NC
International Classification:
G11C 800
US Classification:
365233
Abstract:
A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.

Voltage Pump For Integrated Circuit And Operating Method Thereof

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US Patent:
60231874, Feb 8, 2000
Filed:
Dec 23, 1997
Appl. No.:
8/997541
Inventors:
Stephen Camacho - Durham NC
Robert Walker - Rougemont NC
Tim Lao - San Jose CA
Assignee:
Mitsubishi Semiconductor America, Inc. - Durham NC
International Classification:
G05F 110
US Classification:
327536
Abstract:
One embodiment of an apparatus for generating a boosted voltage to drive a data signal comprises a voltage pump that includes a driver coupled to an input signal for generating the boosted voltage signal from the input signal; a capacitor coupled to the data signal that stores a charge thereof; and an output transistor that delivers an incremental charge to the driver when the drive signal is asserted. Thus, the boosted voltage signal compensates for a change in logic level of the drive signal. In another embodiment, the apparatus also has gates for combining a plurality of data signals into a single disable-on-low signal. The disable-on-low signal is coupled to the output transistor. When all the data signals are at a low logic level, the disable-on-low signal turns off the output transistor, disabling the circuit. As a result, the circuit conserves power by generating the boosted voltage signal only when needed.

Memory Device That Supports Multiple Memory Configurations

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US Patent:
20170062039, Mar 2, 2017
Filed:
Aug 26, 2015
Appl. No.:
14/835986
Inventors:
- Pleasanton CA, US
Byeong Cheol Na - Tracy CA, US
Tim Lao - Sacramento CA, US
International Classification:
G11C 11/4074
G11C 11/4093
G11C 17/16
G11C 17/18
G11C 29/50
G11C 11/4091
Abstract:
A memory device comprises: a plurality of memory configuration modes; an option selection logic for selecting one of the plurality of memory configuration modes to operate the memory device; and bonding pads. The bonding pads are connected to inputs of the option selection logic. The bonding pads are configurable to allow for a default mode selection for the selected one of the plurality of memory configuration modes to operate the memory device.
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Tim P Lao from Sacramento, CA, age ~56 Get Report