Timothy T Chang

6975956, Dec 13, 2005

Sep 19, 2002

10/247188

Timothy C. Chang - Saratoga CA, US
Donald C. Stark - Los Altos Hills CA, US

Rambus Inc. - Los Altos CA

G06F019/00

702120

An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

7162672, Jan 9, 2007

Sep 14, 2001

09/953486

Carl W. Werner - Los Gatos CA, US
Jared L. Zerbe - Woodside CA, US
William F. Stonecypher - San Jose CA, US
Haw-Jyh Liaw - Fremont CA, US
Timothy C. Chang - Saratoga CA, US

Rambus Inc - Los Altos CA

G01R 31/28
G01R 31/02

714724, 324765, 324763, 326 16

Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.

7331006, Feb 12, 2008

Aug 10, 2005

11/201609

Timothy C. Chang - Saratoga CA, US
Donald C. Stark - Los Altos Hills CA, US

Rambus Inc. - Los Altos CA

G01R 31/3183
G01R 31/40

714735, 714738

An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

7592824, Sep 22, 2009

Jan 30, 2004

10/768443

Frederick Ware - Los Altos Hills CA, US
Scott Best - Palo Alto CA, US
Timothy Chang - Saratoga CA, US
Richard Perego - San Jose CA, US
Ely Tsern - Los Altos CA, US
Jeff Mitchell - Santa Clara CA, US

Rambus Inc. - Los Altos CA

G01R 31/02
G01R 31/28

324763

A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

8278964, Oct 2, 2012

Sep 4, 2009

12/554840

Frederick Ware - Los Altos Hills CA, US
Scott Best - Palo Alto CA, US
Timothy Chang - Saratoga CA, US
Richard Perego - San Jose CA, US
Ely Tsern - Los Altos CA, US
Jeff Mitchell - Santa Clara CA, US

Rambus Inc. - Sunnyvale CA

G01R 31/28

32476301, 324500, 3247503

A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.

20190075689, Mar 7, 2019

Aug 31, 2018

16/118526

- Cupertino CA, US
Laura M. Campo - Santa Clara CA, US
Timothy Y. Chang - Sunnyvale CA, US
Holly E. Gerhard - Cupertino CA, US
Fletcher R. Rothkopf - Sunnyvale CA, US
Jae Hwang Lee - Los Gatos CA, US

H05K 7/20

A head-mounted display to be worn by a user includes a housing, a component chamber defined in the housing, and electronic components that generate heat. The electronic components are located in the component chamber of the housing. The head-mounted display also includes a first fan for causing air to flow through the component chamber.

20180263568, Sep 20, 2018

Mar 9, 2018

15/917494

- Stanford CA, US
Timothy Chan Chang - Mountain View CA, US
Joseph Chihping Liao - Stanford CA, US
Daniel L. Rubin - Palo Alto CA, US

The Board of Trustees of the Leland Stanford Junior University - Stanford CA

A61B 5/00
G06T 7/00
A61B 1/00
A61B 5/20
A61B 1/04

Systems and methods for performing image processing in accordance with embodiments of the invention are illustrated. One embodiment includes an imaging system including at least one processor, an input/output interface in communication with a medical imaging device, a display in communication with the processor, and a memory in communication with the processor, including image data obtained from a medical imaging device, where the image data describes at least one image describing at least one region of a patient's body, and an image processing application, where the image processing application directs the processor to preprocess the image data, identify pathological features within the preprocessed image data, calculate the likelihood that the at least one region described by the at least one image is afflicted by a disease, and provide a disease classification substantially instantaneously describing the disease and the likelihood of the disease being present in the region via the display.