Search

Venkatesh Seetharam

from Fremont, CA
Age ~43
Get Report
Also known as:
Venkatesh M, H M
Connected to:
Arun S Seetharaman, 49Jayashree J SeetharamanSrini W Seetharam, 53Kalpana Seethepalli, 49Murali S Seethuraman, 44Jason R Seetin, 50Jon P Seetin, 79Gary D Seever, 67Timothy S Seevers, 58Marilyn D Seewagen, 47

Venkatesh Seetharam Phones & Addresses

  • Fremont, CA
  • Sunnyvale, CA
  • San Jose, CA
  • Clemson, SC

Work

Company: Broadcom Feb 1, 2016 Position: Principal si and emi engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Clemson University 2002 to 2007 Specialities: Electrical Engineering

Skills

Signal Integrity • Simulations • Electromagnetics • Ansys • Pcb Design • Eda • Hardware Architecture • Rf • Semiconductors • Circuit Design • Electronics • Spice • Electrical Engineering • Matlab • Microwave • R&D • Agilent Ads • Spectrum Analyzer

Languages

Tamil

Industries

Computer Software

Resumes

Resumes

Venkatesh Seetharam Photo 1

Principal Si And Emi Engineer

View page
Location:
San Francisco, CA
Industry:
Computer Software
Work:
Broadcom
Principal Si and Emi Engineer
Avago Technologies May 2014 - Jan 2016
Principal Si and Emi Engineer
Avago Technologies May 2012 - May 2014
Senior R and D Emi and Si Engineer
Avago Technologies Sep 2011 - Apr 2012
Senior Si Applications Engineer
Ansys, Inc. Nov 2007 - Sep 2011
Application Engineer Ii
Education:
Clemson University 2002 - 2007
Doctorates, Doctor of Philosophy, Electrical Engineering
Skills:
Signal Integrity
Simulations
Electromagnetics
Ansys
Pcb Design
Eda
Hardware Architecture
Rf
Semiconductors
Circuit Design
Electronics
Spice
Electrical Engineering
Matlab
Microwave
R&D
Agilent Ads
Spectrum Analyzer
Languages:
Tamil

Publications

Us Patents

Bond Wire Arrangement For Minimizing Crosstalk

View page
US Patent:
8558398, Oct 15, 2013
Filed:
Oct 22, 2012
Appl. No.:
13/656858
Inventors:
- Singapore, SG
Venkatesh Seetharam - Fremont CA, US
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd. - Singapore
International Classification:
H01L 23/52
US Classification:
257784, 438617
Abstract:
A lead frame assembly for an integrated circuit package includes a lead frame, a die, first and second information signal-carrying bond wires, first and second ground bond wires, and first and second ground down bond wires. Each ground bond wire shares a die pad with one of the ground down bond wires.

Emi Shield To Suppress Emi Leakage From One Or More Optical Ports Of An Optical Communications Module

View page
US Patent:
20170059798, Mar 2, 2017
Filed:
Aug 28, 2015
Appl. No.:
14/839107
Inventors:
- Singapore, SG
Frank Yashar - Cupertino CA, US
Venkatesh Seetharam - Fremont CA, US
Sunil Priyadarshi - Sunnyvale CA, US
International Classification:
G02B 6/42
H05K 9/00
H05K 5/04
Abstract:
In one exemplary embodiment, an optical communications module includes an upper housing portion mated to a lower housing portion with an optical port projecting through an opening in a front surface of the mated assembly. Electronic circuit housed inside the mated assembly can lead to electromagnetic interference (EMI) leakage through a front surface of the mated assembly, especially through the opening that accommodates the optical port. An EMI shield, which is used to address the EMI leakage, includes an annular array of resilient metal fingers that press against a metal flange of the optical port, and also includes at least two peripheral edges each incorporating an array of resilient metal fingers that press against a metal portion of the mated assembly. An interdigital spacing in the annular array and/or the array of resilient metal fingers is defined on the basis of a wavelength associated with the EMI radiation.
Control profile
Venkatesh Seetharam from Fremont, CA, age ~43 Get Report