Vijayanand J Angarai

7607057, Oct 20, 2009

Dec 28, 2004

11/023731

Mark Allen Boike - Plano TX, US
Seshagiri Prasad Kalluri - Richardson TX, US
Vijayanand J. Angarai - Richardson TX, US
David Mark Brantley - Flower Mound TX, US
Scott Avery Beeker - Coppell TX, US

LSI Corporation - Milpitas CA

G01R 31/28

714727, 714 30, 714724, 714729, 716 4

An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is embedded in the SOC. The test wrapper includes a scan chain. The test wrapper surrounds inputs and outputs of the hard macro. The test wrapper receives a known test data pattern in the scan chain that is included in the test wrapper. The hard macro receives from the test wrapper a set of non-test standard SOC inputs when the SOC is not in a test mode and receives the known test data pattern when the SOC is in the test mode. The hard macro generates a set of outputs in response to the inputs. The hard macro is tested utilizing the known test data pattern.

8095781, Jan 10, 2012

Sep 4, 2008

12/204769

Vijayanand Angarai - Allen TX, US
Michelle Y. Che - Richardson TX, US
Asheesh Kashyap - Plano TX, US
Tracy Nguyen - The Colony TX, US

Verisilicon Holdings Co., Ltd. - Santa Clara CA

G06F 9/35
G06F 9/355

712220, 712235

A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop instruction, and b) provide a tight loop instruction target address. The next PC value generator further includes a next PC value logic having a plurality of inputs: a first input coupled to an output of the discontinuity decoder, and a second input coupled to an output of the tight loop decoder. The next PC value logic provides as an output, without a stall, a control signal that a next PC value is to be loaded with the tight loop instruction target address if: the discontinuity decoder detects a discontinuity instruction, and the tight loop decoder detects a tight loop instruction.

6622154, Sep 16, 2003

Dec 21, 1999

09/467939

Naoki Hayashi - Dallas TX
Vijayanand Angarai - Dallas TX

LSI Logic Corporation - Milpitas CA

G06F 752

708620, 708628

In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

20190073014, Mar 7, 2019

Sep 7, 2017

15/698230

- Plano TX, US
Vijayanand Angarai - Allen TX, US
Adam Christopher Krolnik - Wylie TX, US
Venkata Krishna Vemireddy - San Jose CA, US

G06F 1/32
H04L 29/08

A data collection system includes one or more input sensing devices and a data collection device. The data collection device includes data collection circuitry that is continuously activated to capture measurement data samples from the one or more input sensing devices and locally store the measurement data samples. The data collection device also includes a digital processor that is coupled to the data collection circuitry and is activated to locally perform a sample analysis of the measurement data samples, wherein the sample analysis is a regular analysis of routine measurement data samples when the measurement data samples are without a triggering event, and wherein the sample analysis is an event analysis when the measurement data samples include a triggering event. A data collection integrated circuit and a measurement data sample collection method are also included.