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Wayne A Thorsted

from Longmont, CO
Age ~75
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Also known as:
Wayne Aaron Thorsted, Wayne Thorsted Living, Wayne D
Phone and address:
2401 24Th Ave, Longmont, CO 80503
(303) 684-0638
Related to:
Michael John Sims, 66Janet Sims, 60Janet S, 62Taylor SimsRebecca Wall, 75Courtney Sims
Connected to:
Brandon E Thorsten, 51Brian J Thorstenson, 63Chris W Thorstensen, 43Eric E Thorstenberg, 72Gregory J Thorsteinson, 35Heidi R Thorstenson, 52Karen E Thorsted, 68Thor Thorsteinsson, 34Kelsey S Thorton, 40Martin Thorton

Wayne Thorsted Phones & Addresses

  • 2401 24Th Ave, Longmont, CO 80503 (303) 684-0638 (303) 684-0639
  • 1610 Heirloom Way, Longmont, CO 80501 (303) 684-0638
  • Berthoud, CO
  • Lyons, CO
  • Ogden, UT
  • Colorado Springs, CO
  • Bountiful, UT
  • Aurora, CO

Work

Position: Currently looking for a new opportunity in the storage industry

Education

Degree: Bachelors, Bachelor of Science School / High School: Utah State University 1970 to 1973 Specialities: Computer Science

Skills

Firmware • Debugging • Scsi • Asic • Embedded Systems • Soc • Sata • Processors • Verilog • Arm • Embedded Software • Storage • Ssd • Fpga • Semiconductors • Device Drivers • Hardware Architecture • Ic • Testing • System Architecture • Perl • Rtos • Hardware • Hard Drives • C • Arm Assembly • Spi • Uart • Nand Flash • Lauterbach • Debuggers • Boot Rom • Microprocessors • System on A Chip • Serial Ata

Industries

Writing And Editing

Resumes

Resumes

Wayne Thorsted Photo 1

Currently Looking For A New Opportunity In The Storage Industry

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Location:
Longmont, CO
Industry:
Writing And Editing
Work:

Currently Looking For A New Opportunity In the Storage Industry
Encore Semi Apr 2016 - Sep 2017
Contractor - Senior Firmware Engineer
Western Digital Jun 2008 - Dec 2015
Senior Principal Engineer
Stmicroelectronics Jan 1999 - Jun 2008
Senior Principal Firmware Engineer
Adaptec 1993 - 1999
Principal Firmware Engineer
Education:
Utah State University 1970 - 1973
Bachelors, Bachelor of Science, Computer Science Box Elder High School 1964 - 1967
Skills:
Firmware
Debugging
Scsi
Asic
Embedded Systems
Soc
Sata
Processors
Verilog
Arm
Embedded Software
Storage
Ssd
Fpga
Semiconductors
Device Drivers
Hardware Architecture
Ic
Testing
System Architecture
Perl
Rtos
Hardware
Hard Drives
C
Arm Assembly
Spi
Uart
Nand Flash
Lauterbach
Debuggers
Boot Rom
Microprocessors
System on A Chip
Serial Ata

Publications

Us Patents

Defective Data Sector Management System

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US Patent:
6526476, Feb 25, 2003
Filed:
Feb 26, 1999
Appl. No.:
09/257685
Inventors:
Aaron Wade Wilson - Berthoud CO
Wayne Aaron Thorsted - Longmont CO
Assignee:
STMicroelectronics N.V.
International Classification:
G06F 1200
US Classification:
711112, 711114, 711165, 711170, 711173, 714 6, 714 7, 714 8, 3692753
Abstract:
a firm ware based technique related to managing defective data sector information in a disk drive. Specially, technique provides for a dynamic method by which the number of spare or served alternate sectors and their locations can be allocated in the event defective data sectors exist. One advantage of the present invention exists for certain applications where the capacity and/or configuration of the drive are configured at run time. The present invention also has the advantage of improving performance when accessing âgrownâ defects by allowing the block relocation information to be placed physically closer to the location of the defective blocks.

Disk Drive Booting From Volatile Semiconductor Memory When Exiting Power Save Mode

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US Patent:
8601248, Dec 3, 2013
Filed:
Mar 28, 2011
Appl. No.:
13/073032
Inventors:
Wayne A. Thorsted - Berthoud CO, US
Assignee:
Western Digital Technologies, Inc. - Irvine CA
International Classification:
G06F 1/32
G06F 15/177
US Classification:
713 1, 713 2, 713320
Abstract:
A disk drive is disclosed comprising a head actuated over a disk, a first volatile semiconductor memory (VSM), and a second VSM. When the disk drive is powered on, control circuitry first reads VSM initialization code from the disk, first initializes the first VSM using the VSM initialization code, stores the VSM initialization code in the second VSM, and then enters a power save mode. When exiting the power save mode, the control circuitry second initializes the first VSM using the VSM initialization code stored in the second VSM.

Method And Apparatus For Optimizing Prefetch Caching By Reverse Ordering Of Logical Blocks

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US Patent:
52838757, Feb 1, 1994
Filed:
Apr 13, 1990
Appl. No.:
7/509037
Inventors:
Kenneth J. Gibson - Monument CO
James P. Jackson - Colorado Springs CO
Richard F. Lary - Colorado Springs CO
Wayne A. Thorsted - Colorado Springs CO
Assignee:
Digital Equipment Corporation - Maynard MA
International Classification:
G06F 1200
G06F 1208
G06F 1206
US Classification:
395400
Abstract:
Methods and apparatus for optimizing prefetch caching for sets of disc drives with reverse ordered logical block mapping.

Servo Error Response System On A Magnetic Disk Device

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US Patent:
60645350, May 16, 2000
Filed:
Aug 14, 1997
Appl. No.:
8/911097
Inventors:
Aaron W. Wilson - Berthoud CO
Russell B. Josephson - Berthoud CO
Wen Lin - Niwot CO
Wayne A. Thorsted - Longmont CO
Assignee:
STMicroelectronics, N.V.
International Classification:
G11B 1504
US Classification:
360 60
Abstract:
A system for halting operation of a hard disk controller when a write operation occurs during a servo positioning error condition including a memory cell for retaining an indication of whether a write operation occurred during the previous servo sector. A memory cell, such as a flip flop, is set on any occurrence of a write operation. With the reading of a next servo field, the output of the first flip flop is latched to a second flip flop. During a present servo sector, a servo positioning error signal is logically AND'ed with a write gate active signal where the write gate active signal is enabled if write gate is active in the present servo sector or write gate was active in the previous servo sector (as indicated by the output from the second flip flop.
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Wayne A Thorsted from Longmont, CO, age ~75 Get Report