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Yair E Aizenberg

from Irvine, CA
Age ~56
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Related to:
Tom Aizenberg, 25Evelyn A Aizenberg, 56
Connected to:
David R Aizer, 49Mary J Aizkalns, 68Silvia S Aizprua, 52Ignacio Aizpurua, 94Melida A Aizpurua, 59Joseph Aj, 49Agustin Aja, 103Esther M Aja, 97Henry A Aja, 70Julio F Aja, 75

Yair Aizenberg Phones & Addresses

  • 1 Altair, Irvine, CA 92603
  • 2480 Irvine Blvd, Tustin, CA 92782 (714) 368-9506 (714) 544-4801
  • Red Bank, NJ
  • Sunnyvale, CA
  • Orange, CA
  • Cupertino, CA

Work

Company: Broadcom 2007 Position: Sr. manager, engineering

Skills

ASIC • IC • Semiconductors • SoC • RTL design • Verilog • Digital Design • ARM

Industries

Semiconductors

Resumes

Resumes

Yair Aizenberg Photo 1

Sr. Manager, Engineering At Broadcom Corp.

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Position:
Sr. Manager, Engineering at Broadcom
Location:
Greater Los Angeles Area
Industry:
Semiconductors
Work:
Broadcom since 2007
Sr. Manager, Engineering
Infineon Technologies 2006 - 2007
ASIC Group Manager
PMC-Sierra (Passave networks) 2004 - 2005
Director of VLSI
GlobespanVirata 1997 - 2004
Director, Digital LSI
Zapex 1996 - 1997
Sr. Design Engineer
Skills:
ASIC
IC
Semiconductors
SoC
RTL design
Verilog
Digital Design
ARM

Publications

Us Patents

Circuit And Method For Computing A Fast Fourier Transform

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US Patent:
6477554, Nov 5, 2002
Filed:
Sep 17, 1999
Appl. No.:
09/398636
Inventors:
Yair Aizenberg - Tinton Falls NJ
Daniel Amrany - Ocean Township NJ
Assignee:
GlobespanVirata, Inc. - Red Bank NJ
International Classification:
G06F 1714
US Classification:
708404
Abstract:
A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2s compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Method For Computing A Fast Fourier Transform And Associated Circuit For Addressing A Data Memory

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US Patent:
6490672, Dec 3, 2002
Filed:
May 14, 1999
Appl. No.:
09/311964
Inventors:
Yair Aizenberg - Tinton Falls NJ
Assignee:
GlobespanVirata, Inc. - Red Bank NJ
International Classification:
G06F 1200
US Classification:
711211, 708403
Abstract:
The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage.

Circuit And Method For Computing A Fast Fourier Transform

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US Patent:
6615227, Sep 2, 2003
Filed:
Sep 19, 2002
Appl. No.:
10/247144
Inventors:
Yair Aizenberg - Tinton Falls NJ
Daniel Amrany - Ocean NJ
Assignee:
Globespanvirata, Inc. - Red Bank NJ
International Classification:
G06F 1714
US Classification:
708404
Abstract:
A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2s compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Method For Computing A Fast Fourier Transform And Associated Circuit For Addressing A Data Memory

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US Patent:
6629117, Sep 30, 2003
Filed:
Jun 5, 2002
Appl. No.:
10/126602
Inventors:
Yair Aizenberg - Tinton Falls NJ
Assignee:
Globespanvirata, Inc. - Red Bank NJ
International Classification:
G06F 1714
US Classification:
708404
Abstract:
The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage.

Apparatus And System For Blocking Memory Access During Dma Transfer

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US Patent:
6662245, Dec 9, 2003
Filed:
Jul 25, 2001
Appl. No.:
09/912993
Inventors:
Yair Aizenberg - Tustin CA
Laurent Alloin - Monmouth Beach NJ
Peter Kleewein - Eatontown NJ
Yong Je Lim - Tinton Falls NJ
Assignee:
Globespanvirata, Inc. - Red Bank NJ
International Classification:
G06F 1314
US Classification:
710 22, 710 26, 710 28
Abstract:
The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engines request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Method For Computing A Fast Fourier Transform And Associated Circuit For Addressing A Data Memory

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US Patent:
20020199078, Dec 26, 2002
Filed:
Jul 18, 2002
Appl. No.:
10/198896
Inventors:
Yair Aizenberg - Tinton Falls NJ, US
International Classification:
G06F012/00
US Classification:
711/211000, 711/154000
Abstract:
The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way. More particularly, after computing a first set of complex butterfly operations (each having the same twiddle value) in a given computation stage, a first complex butterfly operation (having a different twiddle value) of a second set of complex butterfly operations, is computed in that stage. Thereafter, all remaining complex butterfly operations (having the same value) in that stage will be computed. This methodology will be repeated until all butterfly operations are calculated in each stage. An addressing circuit is also provided for addressing a data memory in a system for computing a FFT, the system having a data memory for storing data values and a coefficient memory for storing coefficient values.

Multi-Mode Buffer For Digital Signal Processor

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US Patent:
6065127, May 16, 2000
Filed:
Sep 14, 1998
Appl. No.:
9/152441
Inventors:
Yair Aizenberg - Tinton Falls NJ
Daniel Amrany - Ocean NJ
Assignee:
Globespan Semiconductor, Inc. - Red Bank NJ
International Classification:
G06F 1338
US Classification:
713401
Abstract:
The present invention is generally directed to a multi-mode buffer that is configurable to control output delivered to an input, with a variable clock cycle delay. For example, the buffer may be controlled, in one mode to deliver input data to an output, at a one clock cycle delay (i. e. , output data at next clock edge). In another mode, the buffer may be controlled to deliver input data to an output, at a two clock cycle delay. In accordance with one aspect of the present invention, the buffer includes a clock input, a data input, a control input, and an output. The input and the output may be of variable bit width. For example, 8 bits, 16 bits, or some other bit width. The buffer further includes circuitry for delivering data on the data input to the output in response to the clock input. In this regard, the buffer includes circuitry responsive to the control input to vary a delay in delivering the data input to the output, such that the delay may be one clock cycle, two clock cycles, or some other desired length.
Control profile
Yair E Aizenberg from Irvine, CA, age ~56 Get Report