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Zhimin Jimmy Ding

from Palo Alto, CA
Age ~53
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Also known as:
Zhimin J Ding, Zhi Ming Bing
Phone and address:
3130 Ramona St, Palo Alto, CA 94306
Related to:
Lilian L Sun, 61June H Ou, 74Li Jiang, 68Hong Jiang, 67Wallace Sun, 75Xiqun Yi, 62
Connected to:
Ang J DingBaoquan Ding, 46Dominique N DingJimin N Ding, 45Jinwen Ding, 64Mae L Ding, 70Mo Z Ding, 49Nicole R Ding, 42Rachel Ding, 49Ran Ding, 37

Zhimin Ding Phones & Addresses

  • 3130 Ramona St, Palo Alto, CA 94306
  • Sunnyvale, CA
  • Cupertino, CA
  • Pleasanton, CA
  • 4039 Lincoln Ave, Oakland, CA 94602
  • 3618 Macarthur Blvd, Oakland, CA 94619 (510) 531-3486
  • 3863 Patterson Ave, Oakland, CA 94619 (510) 531-3486
  • Los Angeles, CA
  • Alameda, CA

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: High school graduate or higher

Resumes

Resumes

Zhimin Ding Photo 1

Principal Ai Processor Architect

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Location:
Sunnyvale, CA
Industry:
Semiconductors
Work:
Toshiba 2013 - Oct 2018
Principle Architect
Tachyum 2013 - Oct 2018
Principal Ai Processor Architect
Microchip Technology 2013 - Oct 2018
Machine Learning Consultant
Sst Feb 2002 - Mar 2013
Chief Architect
Learning Machines Corp Jan 2000 - Feb 2005
Founder and Chief Technology Officer
Education:
University of Illinois at Urbana - Champaign 1991 - 1996
Doctorates, Doctor of Philosophy, Neuroscience Tsinghua University 1987 - 1989
Masters Tsinghua University 1982 - 1987
Bachelor of Engineering, Bachelors
Skills:
System on A Chip
Ai Accelerator Hw
Deep Learning and Ai Algorithms
Enterprise and Data Center
Image Processing
Robotics
Multi Core Processors and Virtualization
Zhimin Ding Photo 2

Zhimin Ding

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Zhimin Ding
President, Owner
LEARNING MACHINES CORPORATION
Child Day Care Services
1155 Pulora Ct, Sunnyvale, CA 94087
(408) 720-1868

Publications

Us Patents

Universal Pointer Implementation Scheme For Uniformly Addressing Distinct Memory Spaces In A Processors Address Space

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US Patent:
6658553, Dec 2, 2003
Filed:
Apr 14, 2000
Appl. No.:
09/548987
Inventors:
Zhimin Ding - Sunnyvale CA
Gregory K. Goodhue - San Jose CA
Ata R. Khan - Saratoga CA
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G06F 1200
US Classification:
712210, 711212, 711215
Abstract:
A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a âuniversalâ memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.

Memory Organization Allowing Single Cycle Pointer Addressing Where The Address Of The Pointer Is Also Contained In One Of The Memory Locations

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US Patent:
7305543, Dec 4, 2007
Filed:
Jul 27, 2004
Appl. No.:
10/566514
Inventors:
Gregory Goodhue - San Jose CA, US
Ata Khan - Saratoga CA, US
Zhimin Ding - Sunnyvale CA, US
Assignee:
NXP B.V. - Eindhoven
International Classification:
G06F 9/00
US Classification:
712220
Abstract:
All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.

Secure Removable Card Having A Plurality Of Integrated Circuit Dies

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US Patent:
7979717, Jul 12, 2011
Filed:
Apr 9, 2008
Appl. No.:
12/100400
Inventors:
Zhimin Ding - Sunnyvale CA, US
Assignee:
Greenliant LLC - Santa Clara CA
International Classification:
G06F 21/00
H04M 1/00
US Classification:
713185, 726 9, 726 20, 455558
Abstract:
A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die. The processor can receive the first encrypted key and can decrypt the first encrypted key to recover the secret key, and can encrypt data with the secret key for communicating along the electrical connections external to the card.

Microcontroller With An Interrupt Structure Having Programmable Priority Levels With Each Priority Level Associated With A Different Register Set

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US Patent:
8392641, Mar 5, 2013
Filed:
May 24, 2010
Appl. No.:
12/785943
Inventors:
Pankaj Shrivastava - San Jose CA, US
Gregory Goodhue - San Jose CA, US
Ata Khan - Saratoga CA, US
Zhimin Ding - Sunnyvale CA, US
Craig MacKenna - Los Gatos CA, US
Assignee:
NXP B.V. - Eindhoven
International Classification:
G06F 13/24
US Classification:
710260, 712228
Abstract:
Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

Method And Apparatus For Multi-Mode Operation In A Semiconductor Circuit

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US Patent:
20040243783, Dec 2, 2004
Filed:
May 30, 2003
Appl. No.:
10/448944
Inventors:
Zhimin Ding - Sunnyvale CA, US
Shane Hollmer - San Jose CA, US
Philip Barnett - Clanfield, GB
International Classification:
G06F012/00
US Classification:
711/170000, 711/154000
Abstract:
A multi-mode architecture is disclosed for a semiconductor circuit, such as a smart card, microcontroller or another single-chip data processing circuit. The disclosed semiconductor circuit supports at least two modes of operation. A memory management unit restricts each application to a predetermined memory range and enforces certain mode-specific restrictions for each memory partition. In a secure kernel mode, all resources and services on the semiconductor circuit, such as special function registers, are accessible. In an application mode, certain special function registers are not accessible (and thus, the resources associated with such special function registers are also not accessible). The operating system is normally executed in a secure kernel mode, where most, if not all resources are accessible. Likewise, a user application is normally executed in a user mode, where certain resources are not accessible. If an application attempts to access a restricted resource in a user mode, a fault interrupt is generated. If a user application needs to access a restricted resource that is only available in the kernel mode, the user application invokes the kernel mode using an interrupt.

Microcontroller With An Interrupt Structure Having Programmable Priority Levels With Each Priority Level Associated With A Different Register Set

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US Patent:
20060206646, Sep 14, 2006
Filed:
Jul 29, 2004
Appl. No.:
10/566515
Inventors:
Pankaj Shrivastava - San Jose CA, US
Gregory Goodhue - San Jose CA, US
Ata Khan - Saratoga CA, US
Zhimin Ding - Sunnyvale CA, US
Craig Mackenna - Los Gatos CA, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G06F 13/24
G06F 13/36
US Classification:
710260000, 710306000
Abstract:
Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor () has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture () is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.

Integrated Microcontroller And Memory With Secure Interface Between System Program And User Operating System And Application

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US Patent:
20060218425, Sep 28, 2006
Filed:
Jan 31, 2006
Appl. No.:
11/345074
Inventors:
Zhimin Ding - Sunnyvale CA, US
Shane Hollmer - San Jose CA, US
Philip Barnett - Clanfield, GB
International Classification:
G06F 1/00
US Classification:
713323000
Abstract:
An integrated circuit device has a processing unit, a memory management unit, and a memory. The memory management unit is interposed between the memory and the processing unit for controlling access to the memory by the processing unit in one of three modes. In a first mode, called the system mode, the processing unit can access a system program stored in the memory for controlling the resources of the integrated circuit device. In a second mode, called the kernel mode, the processing unit can access an operating system program stored in the memory for controlling the of the integrated circuit device, limited by the system program. Finally in a third mode, called the user mode, the processing unit can access an application program stored in the memory for controlling the resources of the integrated circuit device, limited by the operating system program. In another aspect of the invention, when the processing unit accesses either the operating system program or the application program (herein: “non-system program”), the execution of the non-system program can cause a system interrupt causing program execution to revert to the system mode, but to a specified entry address of the system program, wherein after processing the system interrupt, operation returns to the non-system program in either the kernel mode or the user mode.

Removable Card And A Mobile Wireless Communication Device

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US Patent:
20090075698, Mar 19, 2009
Filed:
Sep 14, 2007
Appl. No.:
11/855846
Inventors:
Zhimin Ding - Sunnyvale CA, US
Richard M. Morley - Pleasanton CA, US
Stephen Johnston - Santa Clara CA, US
Bing Yeh - Los Altos Hills CA, US
John E. Berg - Palo Alto CA, US
International Classification:
H04B 1/38
US Classification:
455558
Abstract:
A removable card for use with a mobile wireless communication device has a processor and a non-volatile memory, connected to the processor. The memory has programming code stored configured to be executed by the processor and is operable in one of two modes. In a first mode the card is connected to the device with the card storing information received wirelessly by the device from the Internet. In a second mode the card is connected to a network portal device, which is connected to the Internet, with the card storing information received through the network portal device from the Internet. In another embodiment, the removable card has electrical connections for connecting to a mobile wireless communicating device for use by a user to connect to the Internet. The memory has two portions: a first portion and a second portion with the partitioning being alterable. The processor restricts access to the first portion by the user, while grants access to the second portion to the user. Finally, the present invention relates to a mobile wireless communication device.
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Zhimin Jimmy Ding from Palo Alto, CA, age ~53 Get Report