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Lide Duan

from San Jose, CA
Age ~40
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Also known as:
Duan Lide
Related to:
Duan Lide, 41
Connected to:
Alice M Duan, 100Honggang Duan, 53Huihui Duan, 52Janice Duan, 80Jinyuan J Duan, 62Joe DuanMack Duan, 33Shanlin L Duan, 59Shiteng Duan, 33Stephanie M Duan, 96

Lide Duan Phones & Addresses

  • San Jose, CA
    • s
  • 7008 Rain Creek Pkwy, Austin, TX 78759
  • San Antonio, TX
  • Sunnyvale, CA

Work

Company: Amd Jan 2012 Address: Austin, Texas Area Position: Senior design engineer

Education

Degree: Ph.D School / High School: Louisiana State University (LSU) 2006 to 2011 Specialities: Electrical and Computer Engineering

Skills

High Performance Computing • Computer Architecture • C++ • C • Programming • Algorithms • Gpu

Languages

English • Mandarin

Industries

Computer Software

Resumes

Resumes

Lide Duan Photo 1

Research Scientist

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Location:
Sunnyvale, CA
Industry:
Computer Software
Work:
AMD - Austin, Texas Area since Jan 2012
Senior Design Engineer
Louisiana State University - Baton Rouge, Louisiana Area Aug 2006 - Dec 2011
Research Assistant
Lawrence Livermore National Laboratory - Livermore, CA May 2011 - Aug 2011
Research Intern
Education:
Louisiana State University (LSU) 2006 - 2011
Ph.D, Electrical and Computer Engineering Shanghai Jiao Tong University 2002 - 2006
B.S., Computer Science and Engineering
Skills:
High Performance Computing
Computer Architecture
C++
C
Programming
Algorithms
Gpu
Languages:
English
Mandarin

Publications

Us Patents

Memory System For Accelerating Graph Neural Network Processing

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US Patent:
20230026824, Jan 26, 2023
Filed:
Jul 15, 2022
Appl. No.:
17/866304
Inventors:
- Shangai, CN
Yangjie ZHOU - Shanghai, CN
Lide DUAN - Sunnyvale CA, US
Hongzhong ZHENG - Los Gatos CA, US
International Classification:
G06F 12/0868
G06F 12/0862
Abstract:
A memory system for accelerating graph neural network processing can include an on-host chip memory to cache data needed for processing a current root node. The system can also include a volatile memory interface between the host and non-volatile memory. The volatile memory can be configured to save one or more sets of next root nodes, neighbor nodes and corresponding attributes. The non-volatile memory can have sufficient capacity to store the entire graph data. The non-volatile memory can also be configured to pre-arrange the sets of next root nodes, neighbor nodes and corresponding attributes for storage in the volatile memory.

Method And System For Memory Control

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US Patent:
20210157516, May 27, 2021
Filed:
Nov 27, 2019
Appl. No.:
16/698772
Inventors:
- Grand Cayman, KY
Lide Duan - Sunnyvale CA, US
Yuhao Wang - Sunnyvale CA, US
Xiaoxin Fan - Sunnyvale CA, US
Zhibin Xiao - Sunnyvale CA, US
International Classification:
G06F 3/06
G06F 12/02
Abstract:
Methods and systems are provided for improving memory control. A memory architecture includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured with a Processing-In-Memory (PIM) architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is configured to receive one or more signals from a host via the plurality of lines. The respective memory unit of the plurality of memory units is coupled with a respective line of the plurality of lines, and the respective memory unit is further configured to receive a respective signal of the one or more signals via the interface so as to be individually selected by the host.
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Lide Duan from San Jose, CA, age ~40 Get Report