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Qiuzhen Joe Zou

from Rancho Santa Fe, CA
Age ~50

Qiuzhen Zou Phones & Addresses

  • Rancho Santa Fe, CA
  • 841 Verin Ln, Chula Vista, CA 91910 (858) 381-7595
  • 5791 Rutgers Rd, La Jolla, CA 92037
  • 11507 Westview Pkwy, San Diego, CA 92126
  • Fremont, CA
  • 841 Verin Ln, Chula Vista, CA 91910

Work

Company: Spreadtrum Jun 2011 to Apr 2013 Position: Chief technology officer

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Stanford University 2020 to 2023

Skills

Ip • Wifi • Engineering • Wireless

Industries

Telecommunications

Resumes

Resumes

Qiuzhen Zou Photo 1

Qiuzhen Zou

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Location:
P/O Box 675841, Rancho Santa Fe, CA
Industry:
Telecommunications
Work:
Spreadtrum Jun 2011 - Apr 2013
Chief Technology Officer

Mobilepeak 2010 - 2011
Chairman, President

Mobilepeak 2005 - 2010
Chairman, Chief Technology Officer

Qualcomm 1993 - 2003
Vice President Engineering
Education:
Stanford University 2020 - 2023
Masters, Master of Science In Electrical Engineering
Stanford University 1992 - 1993
Masters, Master of Science In Electrical Engineering, Communications
Southeast University, China 1989 - 1992
Bachelors, Bachelor of Science In Electrical Engineering, Engineering
Skills:
Ip
Wifi
Engineering
Wireless

Business Records

Name / Title
Company / Classification
Phones & Addresses
Qiuzhen Zou
President
MOBILEPEAK SYSTEMS, INC
Business Services
5960 Cornerstone Ct W SUITE 200, San Diego, CA 92121
6044 Cornerstone Ct W, San Diego, CA 92121

Publications

Us Patents

Programmable Matched Filter Searcher

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US Patent:
6363108, Mar 26, 2002
Filed:
Mar 31, 1999
Appl. No.:
09/283010
Inventors:
Avneesh Agrawal - Sunnyvale CA
Qiuzhen Zou - La Jolla CA
Assignee:
Qualcomm Inc. - San Diego CA
International Classification:
H04B 1707
US Classification:
375152, 375343, 708314
Abstract:
A novel and improved method and apparatus for searching is described. Channel data is despread utilizing a matched filter structure. The in-phase and quadrature amplitudes of the despreading delivered to coherent accumulators to sum for a programmable duration of time. The amplitude accumulations are squared and summed to produce an energy measurement. The energy measurement is accumulated for a second programmable time to perform non-coherent accumulation. The resulting value is used to determine the likelihood of a pilot signal at that offset. Each matched filter structure comprises an N-value shift register for receiving data, a programmable bank of taps to perform despreading and optional Walsh decovering, and an adder structure to sum the resulting filter tap calculations.

Variable Length Instruction Decoder

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US Patent:
6425070, Jul 23, 2002
Filed:
Mar 18, 1998
Appl. No.:
09/044086
Inventors:
Qiuzhen Zou - San Diego CA
Gilbert C. Sih - San Diego CA
Inyup Kang - San Diego CA
Quaeed Motiwala - San Diego CA
Deepu John - La Jolla CA
Li Zhang - San Diego CA
Haitao Zhang - La Jolla CA
Assignee:
Qualcomm, Inc. - San Diego CA
International Classification:
G06F 9302
US Classification:
712 35, 712210, 712221, 712223, 712 33, 711201, 711212, 710127, 710126
Abstract:
The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention.

Mixed Analog And Digital Integrated Circuits

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US Patent:
6472747, Oct 29, 2002
Filed:
Mar 2, 2001
Appl. No.:
09/798198
Inventors:
Seyfollah Bazarjani - San Diego CA
Haitao Zhang - San Diego CA
Qiuzhen Zou - La Jolla CA
Sanjay Jha - San Diego CA
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H01L 2334
US Classification:
257724, 257738, 257777, 257784, 257786, 361735, 361760, 361783
Abstract:
Techniques for fabricating analog and digital circuits on separate dies and stacking and integrating the dies within a single package to form a mixed-signal IC that provides many benefits. In one aspect, the analog and digital circuits are implemented on two separate dies using possibly different IC processes suitable for these different types of circuits. The analog and digital dies are thereafter integrated (stacked) and encapsulated within the single package. Bonding pads are provided to interconnect the dies and to connect the dies to external pins. The bonding pads may be located and arranged in a manner to provide the required connectivity while minimizing the amount of die area required to implement the pads. In another aspect, the die-to-die connectivity may be tested in conjunction with a serial bus interface.

Digital Signal Processor Having Multiple Access Registers

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US Patent:
6496920, Dec 17, 2002
Filed:
Mar 18, 1998
Appl. No.:
09/044088
Inventors:
Qiuzhen Zou - San Diego CA, 92126
Gilbert C. Sih - San Diego CA, 92129
Jian Lin - San Diego CA, 92126
International Classification:
G06F 900
US Classification:
712 33, 712 35
Abstract:
A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory.

Offline Page Of Monitoring

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US Patent:
6584313, Jun 24, 2003
Filed:
Apr 5, 2001
Appl. No.:
09/828588
Inventors:
Brian K. Butler - San Diego CA
Haitao Zhang - La Jolla CA
Qiuzhen Zou - San Diego CA
Gilbert C. Sih - San Diego CA
Avneesh Agrawal - Sunnyvale CA
Assignee:
Qualcomm, Incorporated - San Diego CA
International Classification:
H04Q 720
US Classification:
455434, 455458, 375147, 375149, 340 723, 340 728
Abstract:
A novel and improved method for performing paging is described. In one embodiment of the invention a searcher is used to detect spread spectrum signals. Samples received RF signals are stored in a sample buffer. During standby mode, the samples are gathered during paging slots assigned to the mobile. A set of searches are performed on the samples, and if pilot signals are detected additional demodulation is performed to detect paging messages. The resulting set of demodulation data may be combined to increase detection. After a page message has been detected, additional demodulation resources may be activated to processes more complete page messages, or other information channels. In one embodiment of the invention, the searcher includes a demodulator to perform quick page detection without the use of finger elements to reduce idle mode power consumption.

Multiple-Data Bus Architecture For A Digital Signal Processor Using Variable-Length Instruction Set With Single Instruction Simultaneous Control

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US Patent:
6615341, Sep 2, 2003
Filed:
Jun 5, 2001
Appl. No.:
09/876189
Inventors:
Gilbert C. Sih - San Diego CA
Qiuzhen Zou - La Jolla CA
Inyup Kang - San Diego CA
Quaeed Motiwala - San Diego CA
Deepu John - La Jolla CA
Li Zhang - San Diego CA
Haitao Zhang - La Jolla CA
Charles E. Sakamaki - San Diego CA
Prashant A. Kantak - San Diego CA
Sanjay K. Jha - San Diego CA
Jian Lin - San Diego CA
Assignee:
Qualcomm, Inc. - San Diego CA
International Classification:
G06F 9302
US Classification:
712221, 712222, 712 41, 712 33, 712 35, 712 25, 708495, 708204, 708501
Abstract:
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Position Location With Low Tolerance Oscillator

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US Patent:
6665539, Dec 16, 2003
Filed:
Feb 1, 2001
Appl. No.:
09/775895
Inventors:
Gilbert C. Sih - San Diego CA
Qiuzhen Zou - San Diego CA
Assignee:
Qualcomm Inc. - San Diego CA
International Classification:
H04Q 720
US Classification:
4554563, 4554561, 455 85, 455 86
Abstract:
The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method of performing position location in a wireless subscriber unit having a local oscillator, including the steps of receiving a position location request, acquiring a timing signal when a sufficient period of time has elapsed since the local oscillator has been corrected and correcting the local oscillator using a correction signal based on the timing signal, substantially freezing the correction signal, performing a position location procedure using the local oscillator with the correction signal applied, and ending said position location procedure.

Generating And Implementing A Communication Protocol And Interface For High Data Rate Signal Transfer

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US Patent:
6760772, Jul 6, 2004
Filed:
Dec 14, 2001
Appl. No.:
10/020520
Inventors:
Qiuzhen Zou - La Jolla CA
George Alan Wiley - San Diego CA
Brian Steele - Lafayette CO
Assignee:
Qualcomm, Inc. - San Diego CA
International Classification:
G06F 1300
US Classification:
709230
Abstract:
A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range âserialâ type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.
Qiuzhen Joe Zou from Rancho Santa Fe, CA, age ~50 Get Report